   1              		.syntax unified
   2              		.cpu cortex-m3
   3              		.fpu softvfp
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 4
  11              		.eabi_attribute 34, 1
  12              		.eabi_attribute 18, 4
  13              		.thumb
  14              		.syntax unified
  15              		.file	"vic_cortexm3.c"
  16              		.text
  17              	.Ltext0:
  18              		.cfi_sections	.debug_frame
  19              		.section	.text.nmi_ISR,"ax",%progbits
  20              		.align	1
  21              		.weak	nmi_ISR
  22              		.thumb
  23              		.thumb_func
  25              	nmi_ISR:
  26              	.LFB0:
  27              		.file 1 "uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c"
   1:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** #include "vic.h"
   2:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
   3:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** #if (VIC_USE_DEBUG == pdON) || (VICERR_USE_DEBUG == pdON)
   4:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** #include"stdio_uc.h"
   5:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** #endif
   6:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
   7:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
   8:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** typedef void (*void_pFunc_t)(int);
   9:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** static volatile void_pFunc_t vicerr_Functions = NULL;
  10:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
  11:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** extern u32 _stack; // Definido no linkscript
  12:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** extern void _start (void); // definido no startup.c
  13:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
  14:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void nmi_ISR (void) __attribute__((weak));
  15:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void hardFault_ISR (void) __attribute__((weak));
  16:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void memManage_ISR (void) __attribute__((weak));
  17:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void busFault_ISR (void) __attribute__((weak));
  18:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void usageFault_ISR (void) __attribute__((weak));
  19:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void svc_ISR (void) __attribute__((weak));
  20:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void debugMon_ISR (void) __attribute__((weak));
  21:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void pendSV_ISR (void) __attribute__((weak));
  22:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void sysTick_ISR (void) __attribute__((weak));
  23:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
  24:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void wdt_ISR (void) __attribute__((weak));
  25:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void timer0_ISR (void) __attribute__((weak));
  26:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void timer1_ISR (void) __attribute__((weak));
  27:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void timer2_ISR (void) __attribute__((weak));
  28:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void timer3_ISR (void) __attribute__((weak));
  29:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void uart0_ISR (void) __attribute__((weak));
  30:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void uart1_ISR (void) __attribute__((weak));
  31:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void uart2_ISR (void) __attribute__((weak));
  32:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void uart3_ISR (void) __attribute__((weak));
  33:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void pwm_ISR (void) __attribute__((weak));
  34:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void i2c0_ISR (void) __attribute__((weak));
  35:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void i2c1_ISR (void) __attribute__((weak));
  36:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void i2c2_ISR (void) __attribute__((weak));
  37:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void spi_ISR (void) __attribute__((weak));
  38:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void ssp0_ISR (void) __attribute__((weak));
  39:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void ssp1_ISR (void) __attribute__((weak));
  40:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void pll0_ISR (void) __attribute__((weak));
  41:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void rtc_ISR (void) __attribute__((weak));
  42:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void eint0_ISR (void) __attribute__((weak));
  43:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void eint1_ISR (void) __attribute__((weak));
  44:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void eint2_ISR (void) __attribute__((weak));
  45:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void eint3_ISR (void) __attribute__((weak));
  46:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void adc_ISR (void) __attribute__((weak));
  47:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void bod_ISR (void) __attribute__((weak));
  48:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void usbHost_ISR (void) __attribute__((weak));
  49:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void can_ISR (void) __attribute__((weak));
  50:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void dma_ISR (void) __attribute__((weak));
  51:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void i2s_ISR (void) __attribute__((weak));
  52:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void enet_ISR (void) __attribute__((weak));
  53:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void rit_ISR (void) __attribute__((weak));
  54:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void mcpwm_ISR (void) __attribute__((weak));
  55:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void qei_ISR (void) __attribute__((weak));
  56:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void pll1_ISR (void) __attribute__((weak));
  57:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void usbAct_ISR (void) __attribute__((weak));
  58:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void canAct_ISR (void) __attribute__((weak));
  59:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void uart4_ISR (void) __attribute__((weak));
  60:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void ssp2_ISR (void) __attribute__((weak));
  61:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void lcd_ISR (void) __attribute__((weak));
  62:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void gpio_ISR (void) __attribute__((weak));
  63:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void pwm0_ISR (void) __attribute__((weak));
  64:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void eeprom_ISR (void) __attribute__((weak));
  65:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
  66:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** __attribute__ ((section(".vectors"), used))
  67:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void (* const gVectors[])(void) =
  68:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** {
  69:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    // 16 VETORES DE INTERRUPÇÃO DE SISTEMA
  70:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	(void (*)(void))((unsigned long)&_stack),
  71:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    _start,
  72:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    nmi_ISR,
  73:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    hardFault_ISR,
  74:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    memManage_ISR,
  75:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    busFault_ISR,
  76:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    usageFault_ISR,
  77:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    0, 0, 0, 0,
  78:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    svc_ISR,
  79:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    debugMon_ISR,
  80:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    0,
  81:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    pendSV_ISR,
  82:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    sysTick_ISR,
  83:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
  84:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    // 16 VETORES DE INTERRUPÇÃO DE SISTEMA
  85:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    wdt_ISR,
  86:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    timer0_ISR,
  87:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    timer1_ISR,
  88:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    timer2_ISR,
  89:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    timer3_ISR,
  90:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    uart0_ISR,
  91:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    uart1_ISR,
  92:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    uart2_ISR,
  93:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    uart3_ISR,
  94:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    pwm_ISR,
  95:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    i2c0_ISR,
  96:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    i2c1_ISR,
  97:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    i2c2_ISR,
  98:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    spi_ISR,
  99:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    ssp0_ISR,
 100:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    ssp1_ISR,
 101:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    pll0_ISR,
 102:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    rtc_ISR,
 103:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    eint0_ISR,
 104:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    eint1_ISR,
 105:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    eint2_ISR,
 106:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    eint3_ISR,
 107:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    adc_ISR,
 108:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    bod_ISR,
 109:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    usbHost_ISR,
 110:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    can_ISR,
 111:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    dma_ISR,
 112:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    i2s_ISR,
 113:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    enet_ISR,
 114:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    rit_ISR,
 115:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    mcpwm_ISR,
 116:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    qei_ISR,
 117:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    pll1_ISR,
 118:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    usbAct_ISR,
 119:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    canAct_ISR,
 120:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    uart4_ISR,
 121:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    ssp2_ISR,
 122:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    lcd_ISR,
 123:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    gpio_ISR,
 124:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    pwm0_ISR,
 125:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****    eeprom_ISR
 126:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }; /* gVectors */
 127:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 128:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** /*
 129:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****  * And here are the weak interrupt handlers.
 130:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c ****  */
 131:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void nmi_ISR (void) {
  28              		.loc 1 131 0
  29              		.cfi_startproc
  30              		@ args = 0, pretend = 0, frame = 0
  31              		@ frame_needed = 0, uses_anonymous_args = 0
  32 0000 08B5     		push	{r3, lr}
  33              	.LCFI0:
  34              		.cfi_def_cfa_offset 8
  35              		.cfi_offset 3, -8
  36              		.cfi_offset 14, -4
 132:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 133:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr NMI");
  37              		.loc 1 133 0
  38 0002 0549     		ldr	r1, .L7
  39 0004 0220     		movs	r0, #2
  40 0006 FFF7FEFF 		bl	rprintf
  41              	.LVL0:
 134:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 135:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(1);
  42              		.loc 1 135 0
  43 000a 044B     		ldr	r3, .L7+4
  44 000c 1A68     		ldr	r2, [r3]
  45 000e 12B1     		cbz	r2, .L2
  46              		.loc 1 135 0 is_stmt 0 discriminator 1
  47 0010 1B68     		ldr	r3, [r3]
  48 0012 0120     		movs	r0, #1
  49 0014 9847     		blx	r3
  50              	.LVL1:
  51              	.L2:
  52              	.L5:
  53 0016 FEE7     		b	.L5
  54              	.L8:
  55              		.align	2
  56              	.L7:
  57 0018 00000000 		.word	.LC0
  58 001c 00000000 		.word	.LANCHOR0
  59              		.cfi_endproc
  60              	.LFE0:
  62              		.section	.text.hardFault_ISR,"ax",%progbits
  63              		.align	1
  64              		.weak	hardFault_ISR
  65              		.thumb
  66              		.thumb_func
  68              	hardFault_ISR:
  69              	.LFB1:
 136:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 137:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 138:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 139:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void hardFault_ISR (void) {
  70              		.loc 1 139 0 is_stmt 1
  71              		.cfi_startproc
  72              		@ args = 0, pretend = 0, frame = 0
  73              		@ frame_needed = 0, uses_anonymous_args = 0
  74 0000 08B5     		push	{r3, lr}
  75              	.LCFI1:
  76              		.cfi_def_cfa_offset 8
  77              		.cfi_offset 3, -8
  78              		.cfi_offset 14, -4
 140:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 141:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr hardFault"CMD_TERMINATOR);
  79              		.loc 1 141 0
  80 0002 0D49     		ldr	r1, .L14
  81 0004 0220     		movs	r0, #2
  82 0006 FFF7FEFF 		bl	rprintf
  83              	.LVL2:
 142:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("Possiveis causas:"CMD_TERMINATOR);
  84              		.loc 1 142 0
  85 000a 0C49     		ldr	r1, .L14+4
  86 000c 0220     		movs	r0, #2
  87 000e FFF7FEFF 		bl	rprintf
  88              	.LVL3:
 143:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("  Acesso a um hardware não ligado ou com clock desligado"CMD_TERMINATOR);
  89              		.loc 1 143 0
  90 0012 0B49     		ldr	r1, .L14+8
  91 0014 0220     		movs	r0, #2
  92 0016 FFF7FEFF 		bl	rprintf
  93              	.LVL4:
 144:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("  Acesso a memória inexistente"CMD_TERMINATOR);
  94              		.loc 1 144 0
  95 001a 0A49     		ldr	r1, .L14+12
  96 001c 0220     		movs	r0, #2
  97 001e FFF7FEFF 		bl	rprintf
  98              	.LVL5:
 145:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("  Registrador acessando pino I/O apontando para duas funções diferentes"CMD_TERMINATOR);
  99              		.loc 1 145 0
 100 0022 0949     		ldr	r1, .L14+16
 101 0024 0220     		movs	r0, #2
 102 0026 FFF7FEFF 		bl	rprintf
 103              	.LVL6:
 146:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 147:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(2);
 104              		.loc 1 147 0
 105 002a 084B     		ldr	r3, .L14+20
 106 002c 1A68     		ldr	r2, [r3]
 107 002e 12B1     		cbz	r2, .L10
 108              		.loc 1 147 0 is_stmt 0 discriminator 1
 109 0030 1B68     		ldr	r3, [r3]
 110 0032 0220     		movs	r0, #2
 111 0034 9847     		blx	r3
 112              	.LVL7:
 113              	.L10:
 114              	.L13:
 115 0036 FEE7     		b	.L13
 116              	.L15:
 117              		.align	2
 118              	.L14:
 119 0038 0B000000 		.word	.LC1
 120 003c 1D000000 		.word	.LC2
 121 0040 30000000 		.word	.LC3
 122 0044 6A000000 		.word	.LC4
 123 0048 8A000000 		.word	.LC5
 124 004c 00000000 		.word	.LANCHOR0
 125              		.cfi_endproc
 126              	.LFE1:
 128              		.section	.text.memManage_ISR,"ax",%progbits
 129              		.align	1
 130              		.weak	memManage_ISR
 131              		.thumb
 132              		.thumb_func
 134              	memManage_ISR:
 135              	.LFB2:
 148:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 149:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 150:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void memManage_ISR (void) {
 136              		.loc 1 150 0 is_stmt 1
 137              		.cfi_startproc
 138              		@ args = 0, pretend = 0, frame = 0
 139              		@ frame_needed = 0, uses_anonymous_args = 0
 140 0000 08B5     		push	{r3, lr}
 141              	.LCFI2:
 142              		.cfi_def_cfa_offset 8
 143              		.cfi_offset 3, -8
 144              		.cfi_offset 14, -4
 151:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 152:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr memManage");
 145              		.loc 1 152 0
 146 0002 0549     		ldr	r1, .L21
 147 0004 0220     		movs	r0, #2
 148 0006 FFF7FEFF 		bl	rprintf
 149              	.LVL8:
 153:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 154:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(3);
 150              		.loc 1 154 0
 151 000a 044B     		ldr	r3, .L21+4
 152 000c 1A68     		ldr	r2, [r3]
 153 000e 12B1     		cbz	r2, .L17
 154              		.loc 1 154 0 is_stmt 0 discriminator 1
 155 0010 1B68     		ldr	r3, [r3]
 156 0012 0320     		movs	r0, #3
 157 0014 9847     		blx	r3
 158              	.LVL9:
 159              	.L17:
 160              	.L20:
 161 0016 FEE7     		b	.L20
 162              	.L22:
 163              		.align	2
 164              	.L21:
 165 0018 D3000000 		.word	.LC6
 166 001c 00000000 		.word	.LANCHOR0
 167              		.cfi_endproc
 168              	.LFE2:
 170              		.section	.text.busFault_ISR,"ax",%progbits
 171              		.align	1
 172              		.weak	busFault_ISR
 173              		.thumb
 174              		.thumb_func
 176              	busFault_ISR:
 177              	.LFB3:
 155:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 156:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 157:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void busFault_ISR (void) {
 178              		.loc 1 157 0 is_stmt 1
 179              		.cfi_startproc
 180              		@ args = 0, pretend = 0, frame = 0
 181              		@ frame_needed = 0, uses_anonymous_args = 0
 182 0000 08B5     		push	{r3, lr}
 183              	.LCFI3:
 184              		.cfi_def_cfa_offset 8
 185              		.cfi_offset 3, -8
 186              		.cfi_offset 14, -4
 158:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 159:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr busFault");
 187              		.loc 1 159 0
 188 0002 0549     		ldr	r1, .L28
 189 0004 0220     		movs	r0, #2
 190 0006 FFF7FEFF 		bl	rprintf
 191              	.LVL10:
 160:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 161:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(4);
 192              		.loc 1 161 0
 193 000a 044B     		ldr	r3, .L28+4
 194 000c 1A68     		ldr	r2, [r3]
 195 000e 12B1     		cbz	r2, .L24
 196              		.loc 1 161 0 is_stmt 0 discriminator 1
 197 0010 1B68     		ldr	r3, [r3]
 198 0012 0420     		movs	r0, #4
 199 0014 9847     		blx	r3
 200              	.LVL11:
 201              	.L24:
 202              	.L27:
 203 0016 FEE7     		b	.L27
 204              	.L29:
 205              		.align	2
 206              	.L28:
 207 0018 E4000000 		.word	.LC7
 208 001c 00000000 		.word	.LANCHOR0
 209              		.cfi_endproc
 210              	.LFE3:
 212              		.section	.text.usageFault_ISR,"ax",%progbits
 213              		.align	1
 214              		.weak	usageFault_ISR
 215              		.thumb
 216              		.thumb_func
 218              	usageFault_ISR:
 219              	.LFB4:
 162:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 163:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 164:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void usageFault_ISR (void) {
 220              		.loc 1 164 0 is_stmt 1
 221              		.cfi_startproc
 222              		@ args = 0, pretend = 0, frame = 0
 223              		@ frame_needed = 0, uses_anonymous_args = 0
 224 0000 08B5     		push	{r3, lr}
 225              	.LCFI4:
 226              		.cfi_def_cfa_offset 8
 227              		.cfi_offset 3, -8
 228              		.cfi_offset 14, -4
 165:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 166:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr usageFault_ISR");
 229              		.loc 1 166 0
 230 0002 0549     		ldr	r1, .L35
 231 0004 0220     		movs	r0, #2
 232 0006 FFF7FEFF 		bl	rprintf
 233              	.LVL12:
 167:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 168:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(5);
 234              		.loc 1 168 0
 235 000a 044B     		ldr	r3, .L35+4
 236 000c 1A68     		ldr	r2, [r3]
 237 000e 12B1     		cbz	r2, .L31
 238              		.loc 1 168 0 is_stmt 0 discriminator 1
 239 0010 1B68     		ldr	r3, [r3]
 240 0012 0520     		movs	r0, #5
 241 0014 9847     		blx	r3
 242              	.LVL13:
 243              	.L31:
 244              	.L34:
 245 0016 FEE7     		b	.L34
 246              	.L36:
 247              		.align	2
 248              	.L35:
 249 0018 F4000000 		.word	.LC8
 250 001c 00000000 		.word	.LANCHOR0
 251              		.cfi_endproc
 252              	.LFE4:
 254              		.section	.text.svc_ISR,"ax",%progbits
 255              		.align	1
 256              		.weak	svc_ISR
 257              		.thumb
 258              		.thumb_func
 260              	svc_ISR:
 261              	.LFB5:
 169:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 170:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 171:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void svc_ISR (void) {
 262              		.loc 1 171 0 is_stmt 1
 263              		.cfi_startproc
 264              		@ args = 0, pretend = 0, frame = 0
 265              		@ frame_needed = 0, uses_anonymous_args = 0
 266 0000 08B5     		push	{r3, lr}
 267              	.LCFI5:
 268              		.cfi_def_cfa_offset 8
 269              		.cfi_offset 3, -8
 270              		.cfi_offset 14, -4
 172:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** #if (VICERR_USE_DEBUG == pdON)
 173:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr svc");
 271              		.loc 1 173 0
 272 0002 0549     		ldr	r1, .L42
 273 0004 0220     		movs	r0, #2
 274 0006 FFF7FEFF 		bl	rprintf
 275              	.LVL14:
 174:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 175:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(6);
 276              		.loc 1 175 0
 277 000a 044B     		ldr	r3, .L42+4
 278 000c 1A68     		ldr	r2, [r3]
 279 000e 12B1     		cbz	r2, .L38
 280              		.loc 1 175 0 is_stmt 0 discriminator 1
 281 0010 1B68     		ldr	r3, [r3]
 282 0012 0620     		movs	r0, #6
 283 0014 9847     		blx	r3
 284              	.LVL15:
 285              	.L38:
 286              	.L41:
 287 0016 FEE7     		b	.L41
 288              	.L43:
 289              		.align	2
 290              	.L42:
 291 0018 0A010000 		.word	.LC9
 292 001c 00000000 		.word	.LANCHOR0
 293              		.cfi_endproc
 294              	.LFE5:
 296              		.section	.text.debugMon_ISR,"ax",%progbits
 297              		.align	1
 298              		.weak	debugMon_ISR
 299              		.thumb
 300              		.thumb_func
 302              	debugMon_ISR:
 303              	.LFB6:
 176:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 177:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 178:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void debugMon_ISR (void) {
 304              		.loc 1 178 0 is_stmt 1
 305              		.cfi_startproc
 306              		@ args = 0, pretend = 0, frame = 0
 307              		@ frame_needed = 0, uses_anonymous_args = 0
 308 0000 08B5     		push	{r3, lr}
 309              	.LCFI6:
 310              		.cfi_def_cfa_offset 8
 311              		.cfi_offset 3, -8
 312              		.cfi_offset 14, -4
 179:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 180:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr debugMon");
 313              		.loc 1 180 0
 314 0002 0549     		ldr	r1, .L49
 315 0004 0220     		movs	r0, #2
 316 0006 FFF7FEFF 		bl	rprintf
 317              	.LVL16:
 181:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 182:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(7);
 318              		.loc 1 182 0
 319 000a 044B     		ldr	r3, .L49+4
 320 000c 1A68     		ldr	r2, [r3]
 321 000e 12B1     		cbz	r2, .L45
 322              		.loc 1 182 0 is_stmt 0 discriminator 1
 323 0010 1B68     		ldr	r3, [r3]
 324 0012 0720     		movs	r0, #7
 325 0014 9847     		blx	r3
 326              	.LVL17:
 327              	.L45:
 328              	.L48:
 329 0016 FEE7     		b	.L48
 330              	.L50:
 331              		.align	2
 332              	.L49:
 333 0018 15010000 		.word	.LC10
 334 001c 00000000 		.word	.LANCHOR0
 335              		.cfi_endproc
 336              	.LFE6:
 338              		.section	.text.pendSV_ISR,"ax",%progbits
 339              		.align	1
 340              		.weak	pendSV_ISR
 341              		.thumb
 342              		.thumb_func
 344              	pendSV_ISR:
 345              	.LFB7:
 183:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 184:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 185:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void pendSV_ISR (void) {
 346              		.loc 1 185 0 is_stmt 1
 347              		.cfi_startproc
 348              		@ args = 0, pretend = 0, frame = 0
 349              		@ frame_needed = 0, uses_anonymous_args = 0
 350 0000 08B5     		push	{r3, lr}
 351              	.LCFI7:
 352              		.cfi_def_cfa_offset 8
 353              		.cfi_offset 3, -8
 354              		.cfi_offset 14, -4
 186:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 187:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr pendSV");
 355              		.loc 1 187 0
 356 0002 0549     		ldr	r1, .L56
 357 0004 0220     		movs	r0, #2
 358 0006 FFF7FEFF 		bl	rprintf
 359              	.LVL18:
 188:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 189:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(8);
 360              		.loc 1 189 0
 361 000a 044B     		ldr	r3, .L56+4
 362 000c 1A68     		ldr	r2, [r3]
 363 000e 12B1     		cbz	r2, .L52
 364              		.loc 1 189 0 is_stmt 0 discriminator 1
 365 0010 1B68     		ldr	r3, [r3]
 366 0012 0820     		movs	r0, #8
 367 0014 9847     		blx	r3
 368              	.LVL19:
 369              	.L52:
 370              	.L55:
 371 0016 FEE7     		b	.L55
 372              	.L57:
 373              		.align	2
 374              	.L56:
 375 0018 25010000 		.word	.LC11
 376 001c 00000000 		.word	.LANCHOR0
 377              		.cfi_endproc
 378              	.LFE7:
 380              		.section	.text.sysTick_ISR,"ax",%progbits
 381              		.align	1
 382              		.weak	sysTick_ISR
 383              		.thumb
 384              		.thumb_func
 386              	sysTick_ISR:
 387              	.LFB8:
 190:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 191:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 192:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void sysTick_ISR (void) {
 388              		.loc 1 192 0 is_stmt 1
 389              		.cfi_startproc
 390              		@ args = 0, pretend = 0, frame = 0
 391              		@ frame_needed = 0, uses_anonymous_args = 0
 392 0000 08B5     		push	{r3, lr}
 393              	.LCFI8:
 394              		.cfi_def_cfa_offset 8
 395              		.cfi_offset 3, -8
 396              		.cfi_offset 14, -4
 193:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 194:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr sysTick");
 397              		.loc 1 194 0
 398 0002 0549     		ldr	r1, .L63
 399 0004 0220     		movs	r0, #2
 400 0006 FFF7FEFF 		bl	rprintf
 401              	.LVL20:
 195:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 196:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(9);
 402              		.loc 1 196 0
 403 000a 044B     		ldr	r3, .L63+4
 404 000c 1A68     		ldr	r2, [r3]
 405 000e 12B1     		cbz	r2, .L59
 406              		.loc 1 196 0 is_stmt 0 discriminator 1
 407 0010 1B68     		ldr	r3, [r3]
 408 0012 0920     		movs	r0, #9
 409 0014 9847     		blx	r3
 410              	.LVL21:
 411              	.L59:
 412              	.L62:
 413 0016 FEE7     		b	.L62
 414              	.L64:
 415              		.align	2
 416              	.L63:
 417 0018 33010000 		.word	.LC12
 418 001c 00000000 		.word	.LANCHOR0
 419              		.cfi_endproc
 420              	.LFE8:
 422              		.section	.text.wdt_ISR,"ax",%progbits
 423              		.align	1
 424              		.weak	wdt_ISR
 425              		.thumb
 426              		.thumb_func
 428              	wdt_ISR:
 429              	.LFB9:
 197:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 198:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 199:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void wdt_ISR (void) {
 430              		.loc 1 199 0 is_stmt 1
 431              		.cfi_startproc
 432              		@ args = 0, pretend = 0, frame = 0
 433              		@ frame_needed = 0, uses_anonymous_args = 0
 434 0000 08B5     		push	{r3, lr}
 435              	.LCFI9:
 436              		.cfi_def_cfa_offset 8
 437              		.cfi_offset 3, -8
 438              		.cfi_offset 14, -4
 200:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 201:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr wdt");
 439              		.loc 1 201 0
 440 0002 0549     		ldr	r1, .L70
 441 0004 0220     		movs	r0, #2
 442 0006 FFF7FEFF 		bl	rprintf
 443              	.LVL22:
 202:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 203:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(10);
 444              		.loc 1 203 0
 445 000a 044B     		ldr	r3, .L70+4
 446 000c 1A68     		ldr	r2, [r3]
 447 000e 12B1     		cbz	r2, .L66
 448              		.loc 1 203 0 is_stmt 0 discriminator 1
 449 0010 1B68     		ldr	r3, [r3]
 450 0012 0A20     		movs	r0, #10
 451 0014 9847     		blx	r3
 452              	.LVL23:
 453              	.L66:
 454              	.L69:
 455 0016 FEE7     		b	.L69
 456              	.L71:
 457              		.align	2
 458              	.L70:
 459 0018 42010000 		.word	.LC13
 460 001c 00000000 		.word	.LANCHOR0
 461              		.cfi_endproc
 462              	.LFE9:
 464              		.section	.text.timer0_ISR,"ax",%progbits
 465              		.align	1
 466              		.weak	timer0_ISR
 467              		.thumb
 468              		.thumb_func
 470              	timer0_ISR:
 471              	.LFB10:
 204:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 205:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 206:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void timer0_ISR (void) {
 472              		.loc 1 206 0 is_stmt 1
 473              		.cfi_startproc
 474              		@ args = 0, pretend = 0, frame = 0
 475              		@ frame_needed = 0, uses_anonymous_args = 0
 476 0000 08B5     		push	{r3, lr}
 477              	.LCFI10:
 478              		.cfi_def_cfa_offset 8
 479              		.cfi_offset 3, -8
 480              		.cfi_offset 14, -4
 207:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 208:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr timer0");
 481              		.loc 1 208 0
 482 0002 0549     		ldr	r1, .L77
 483 0004 0220     		movs	r0, #2
 484 0006 FFF7FEFF 		bl	rprintf
 485              	.LVL24:
 209:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 210:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(11);
 486              		.loc 1 210 0
 487 000a 044B     		ldr	r3, .L77+4
 488 000c 1A68     		ldr	r2, [r3]
 489 000e 12B1     		cbz	r2, .L73
 490              		.loc 1 210 0 is_stmt 0 discriminator 1
 491 0010 1B68     		ldr	r3, [r3]
 492 0012 0B20     		movs	r0, #11
 493 0014 9847     		blx	r3
 494              	.LVL25:
 495              	.L73:
 496              	.L76:
 497 0016 FEE7     		b	.L76
 498              	.L78:
 499              		.align	2
 500              	.L77:
 501 0018 4D010000 		.word	.LC14
 502 001c 00000000 		.word	.LANCHOR0
 503              		.cfi_endproc
 504              	.LFE10:
 506              		.section	.text.timer1_ISR,"ax",%progbits
 507              		.align	1
 508              		.weak	timer1_ISR
 509              		.thumb
 510              		.thumb_func
 512              	timer1_ISR:
 513              	.LFB11:
 211:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 212:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 213:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void timer1_ISR (void) {
 514              		.loc 1 213 0 is_stmt 1
 515              		.cfi_startproc
 516              		@ args = 0, pretend = 0, frame = 0
 517              		@ frame_needed = 0, uses_anonymous_args = 0
 518 0000 08B5     		push	{r3, lr}
 519              	.LCFI11:
 520              		.cfi_def_cfa_offset 8
 521              		.cfi_offset 3, -8
 522              		.cfi_offset 14, -4
 214:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 215:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr timer1");
 523              		.loc 1 215 0
 524 0002 0549     		ldr	r1, .L84
 525 0004 0220     		movs	r0, #2
 526 0006 FFF7FEFF 		bl	rprintf
 527              	.LVL26:
 216:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 217:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(12);
 528              		.loc 1 217 0
 529 000a 044B     		ldr	r3, .L84+4
 530 000c 1A68     		ldr	r2, [r3]
 531 000e 12B1     		cbz	r2, .L80
 532              		.loc 1 217 0 is_stmt 0 discriminator 1
 533 0010 1B68     		ldr	r3, [r3]
 534 0012 0C20     		movs	r0, #12
 535 0014 9847     		blx	r3
 536              	.LVL27:
 537              	.L80:
 538              	.L83:
 539 0016 FEE7     		b	.L83
 540              	.L85:
 541              		.align	2
 542              	.L84:
 543 0018 5B010000 		.word	.LC15
 544 001c 00000000 		.word	.LANCHOR0
 545              		.cfi_endproc
 546              	.LFE11:
 548              		.section	.text.timer2_ISR,"ax",%progbits
 549              		.align	1
 550              		.weak	timer2_ISR
 551              		.thumb
 552              		.thumb_func
 554              	timer2_ISR:
 555              	.LFB12:
 218:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 219:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 220:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void timer2_ISR (void) {
 556              		.loc 1 220 0 is_stmt 1
 557              		.cfi_startproc
 558              		@ args = 0, pretend = 0, frame = 0
 559              		@ frame_needed = 0, uses_anonymous_args = 0
 560 0000 08B5     		push	{r3, lr}
 561              	.LCFI12:
 562              		.cfi_def_cfa_offset 8
 563              		.cfi_offset 3, -8
 564              		.cfi_offset 14, -4
 221:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 222:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr timer2");
 565              		.loc 1 222 0
 566 0002 0549     		ldr	r1, .L91
 567 0004 0220     		movs	r0, #2
 568 0006 FFF7FEFF 		bl	rprintf
 569              	.LVL28:
 223:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 224:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(13);
 570              		.loc 1 224 0
 571 000a 044B     		ldr	r3, .L91+4
 572 000c 1A68     		ldr	r2, [r3]
 573 000e 12B1     		cbz	r2, .L87
 574              		.loc 1 224 0 is_stmt 0 discriminator 1
 575 0010 1B68     		ldr	r3, [r3]
 576 0012 0D20     		movs	r0, #13
 577 0014 9847     		blx	r3
 578              	.LVL29:
 579              	.L87:
 580              	.L90:
 581 0016 FEE7     		b	.L90
 582              	.L92:
 583              		.align	2
 584              	.L91:
 585 0018 69010000 		.word	.LC16
 586 001c 00000000 		.word	.LANCHOR0
 587              		.cfi_endproc
 588              	.LFE12:
 590              		.section	.text.timer3_ISR,"ax",%progbits
 591              		.align	1
 592              		.weak	timer3_ISR
 593              		.thumb
 594              		.thumb_func
 596              	timer3_ISR:
 597              	.LFB13:
 225:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 226:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 227:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void timer3_ISR (void) {
 598              		.loc 1 227 0 is_stmt 1
 599              		.cfi_startproc
 600              		@ args = 0, pretend = 0, frame = 0
 601              		@ frame_needed = 0, uses_anonymous_args = 0
 602 0000 08B5     		push	{r3, lr}
 603              	.LCFI13:
 604              		.cfi_def_cfa_offset 8
 605              		.cfi_offset 3, -8
 606              		.cfi_offset 14, -4
 228:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 229:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr timer3");
 607              		.loc 1 229 0
 608 0002 0549     		ldr	r1, .L98
 609 0004 0220     		movs	r0, #2
 610 0006 FFF7FEFF 		bl	rprintf
 611              	.LVL30:
 230:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 231:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(14);
 612              		.loc 1 231 0
 613 000a 044B     		ldr	r3, .L98+4
 614 000c 1A68     		ldr	r2, [r3]
 615 000e 12B1     		cbz	r2, .L94
 616              		.loc 1 231 0 is_stmt 0 discriminator 1
 617 0010 1B68     		ldr	r3, [r3]
 618 0012 0E20     		movs	r0, #14
 619 0014 9847     		blx	r3
 620              	.LVL31:
 621              	.L94:
 622              	.L97:
 623 0016 FEE7     		b	.L97
 624              	.L99:
 625              		.align	2
 626              	.L98:
 627 0018 77010000 		.word	.LC17
 628 001c 00000000 		.word	.LANCHOR0
 629              		.cfi_endproc
 630              	.LFE13:
 632              		.section	.text.uart0_ISR,"ax",%progbits
 633              		.align	1
 634              		.weak	uart0_ISR
 635              		.thumb
 636              		.thumb_func
 638              	uart0_ISR:
 639              	.LFB14:
 232:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 233:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 234:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void uart0_ISR (void) {
 640              		.loc 1 234 0 is_stmt 1
 641              		.cfi_startproc
 642              		@ args = 0, pretend = 0, frame = 0
 643              		@ frame_needed = 0, uses_anonymous_args = 0
 644 0000 08B5     		push	{r3, lr}
 645              	.LCFI14:
 646              		.cfi_def_cfa_offset 8
 647              		.cfi_offset 3, -8
 648              		.cfi_offset 14, -4
 235:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 236:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr uart0");
 649              		.loc 1 236 0
 650 0002 0549     		ldr	r1, .L105
 651 0004 0220     		movs	r0, #2
 652 0006 FFF7FEFF 		bl	rprintf
 653              	.LVL32:
 237:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 238:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(15);
 654              		.loc 1 238 0
 655 000a 044B     		ldr	r3, .L105+4
 656 000c 1A68     		ldr	r2, [r3]
 657 000e 12B1     		cbz	r2, .L101
 658              		.loc 1 238 0 is_stmt 0 discriminator 1
 659 0010 1B68     		ldr	r3, [r3]
 660 0012 0F20     		movs	r0, #15
 661 0014 9847     		blx	r3
 662              	.LVL33:
 663              	.L101:
 664              	.L104:
 665 0016 FEE7     		b	.L104
 666              	.L106:
 667              		.align	2
 668              	.L105:
 669 0018 85010000 		.word	.LC18
 670 001c 00000000 		.word	.LANCHOR0
 671              		.cfi_endproc
 672              	.LFE14:
 674              		.section	.text.uart1_ISR,"ax",%progbits
 675              		.align	1
 676              		.weak	uart1_ISR
 677              		.thumb
 678              		.thumb_func
 680              	uart1_ISR:
 681              	.LFB15:
 239:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 240:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 241:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void uart1_ISR (void) {
 682              		.loc 1 241 0 is_stmt 1
 683              		.cfi_startproc
 684              		@ args = 0, pretend = 0, frame = 0
 685              		@ frame_needed = 0, uses_anonymous_args = 0
 686 0000 08B5     		push	{r3, lr}
 687              	.LCFI15:
 688              		.cfi_def_cfa_offset 8
 689              		.cfi_offset 3, -8
 690              		.cfi_offset 14, -4
 242:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 243:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr uart1");
 691              		.loc 1 243 0
 692 0002 0549     		ldr	r1, .L112
 693 0004 0220     		movs	r0, #2
 694 0006 FFF7FEFF 		bl	rprintf
 695              	.LVL34:
 244:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 245:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(16);
 696              		.loc 1 245 0
 697 000a 044B     		ldr	r3, .L112+4
 698 000c 1A68     		ldr	r2, [r3]
 699 000e 12B1     		cbz	r2, .L108
 700              		.loc 1 245 0 is_stmt 0 discriminator 1
 701 0010 1B68     		ldr	r3, [r3]
 702 0012 1020     		movs	r0, #16
 703 0014 9847     		blx	r3
 704              	.LVL35:
 705              	.L108:
 706              	.L111:
 707 0016 FEE7     		b	.L111
 708              	.L113:
 709              		.align	2
 710              	.L112:
 711 0018 92010000 		.word	.LC19
 712 001c 00000000 		.word	.LANCHOR0
 713              		.cfi_endproc
 714              	.LFE15:
 716              		.section	.text.uart2_ISR,"ax",%progbits
 717              		.align	1
 718              		.weak	uart2_ISR
 719              		.thumb
 720              		.thumb_func
 722              	uart2_ISR:
 723              	.LFB16:
 246:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 247:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 248:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void uart2_ISR (void) {
 724              		.loc 1 248 0 is_stmt 1
 725              		.cfi_startproc
 726              		@ args = 0, pretend = 0, frame = 0
 727              		@ frame_needed = 0, uses_anonymous_args = 0
 728 0000 08B5     		push	{r3, lr}
 729              	.LCFI16:
 730              		.cfi_def_cfa_offset 8
 731              		.cfi_offset 3, -8
 732              		.cfi_offset 14, -4
 249:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 250:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr uart2");
 733              		.loc 1 250 0
 734 0002 0549     		ldr	r1, .L119
 735 0004 0220     		movs	r0, #2
 736 0006 FFF7FEFF 		bl	rprintf
 737              	.LVL36:
 251:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 252:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(17);
 738              		.loc 1 252 0
 739 000a 044B     		ldr	r3, .L119+4
 740 000c 1A68     		ldr	r2, [r3]
 741 000e 12B1     		cbz	r2, .L115
 742              		.loc 1 252 0 is_stmt 0 discriminator 1
 743 0010 1B68     		ldr	r3, [r3]
 744 0012 1120     		movs	r0, #17
 745 0014 9847     		blx	r3
 746              	.LVL37:
 747              	.L115:
 748              	.L118:
 749 0016 FEE7     		b	.L118
 750              	.L120:
 751              		.align	2
 752              	.L119:
 753 0018 9F010000 		.word	.LC20
 754 001c 00000000 		.word	.LANCHOR0
 755              		.cfi_endproc
 756              	.LFE16:
 758              		.section	.text.uart3_ISR,"ax",%progbits
 759              		.align	1
 760              		.weak	uart3_ISR
 761              		.thumb
 762              		.thumb_func
 764              	uart3_ISR:
 765              	.LFB17:
 253:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 254:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 255:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void uart3_ISR (void) {
 766              		.loc 1 255 0 is_stmt 1
 767              		.cfi_startproc
 768              		@ args = 0, pretend = 0, frame = 0
 769              		@ frame_needed = 0, uses_anonymous_args = 0
 770 0000 08B5     		push	{r3, lr}
 771              	.LCFI17:
 772              		.cfi_def_cfa_offset 8
 773              		.cfi_offset 3, -8
 774              		.cfi_offset 14, -4
 256:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 257:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr uart3");
 775              		.loc 1 257 0
 776 0002 0549     		ldr	r1, .L126
 777 0004 0220     		movs	r0, #2
 778 0006 FFF7FEFF 		bl	rprintf
 779              	.LVL38:
 258:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 259:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(18);
 780              		.loc 1 259 0
 781 000a 044B     		ldr	r3, .L126+4
 782 000c 1A68     		ldr	r2, [r3]
 783 000e 12B1     		cbz	r2, .L122
 784              		.loc 1 259 0 is_stmt 0 discriminator 1
 785 0010 1B68     		ldr	r3, [r3]
 786 0012 1220     		movs	r0, #18
 787 0014 9847     		blx	r3
 788              	.LVL39:
 789              	.L122:
 790              	.L125:
 791 0016 FEE7     		b	.L125
 792              	.L127:
 793              		.align	2
 794              	.L126:
 795 0018 AC010000 		.word	.LC21
 796 001c 00000000 		.word	.LANCHOR0
 797              		.cfi_endproc
 798              	.LFE17:
 800              		.section	.text.pwm_ISR,"ax",%progbits
 801              		.align	1
 802              		.weak	pwm_ISR
 803              		.thumb
 804              		.thumb_func
 806              	pwm_ISR:
 807              	.LFB18:
 260:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 261:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 262:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void pwm_ISR (void) {
 808              		.loc 1 262 0 is_stmt 1
 809              		.cfi_startproc
 810              		@ args = 0, pretend = 0, frame = 0
 811              		@ frame_needed = 0, uses_anonymous_args = 0
 812 0000 08B5     		push	{r3, lr}
 813              	.LCFI18:
 814              		.cfi_def_cfa_offset 8
 815              		.cfi_offset 3, -8
 816              		.cfi_offset 14, -4
 263:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 264:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr pwm");
 817              		.loc 1 264 0
 818 0002 0549     		ldr	r1, .L133
 819 0004 0220     		movs	r0, #2
 820 0006 FFF7FEFF 		bl	rprintf
 821              	.LVL40:
 265:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 266:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(19);
 822              		.loc 1 266 0
 823 000a 044B     		ldr	r3, .L133+4
 824 000c 1A68     		ldr	r2, [r3]
 825 000e 12B1     		cbz	r2, .L129
 826              		.loc 1 266 0 is_stmt 0 discriminator 1
 827 0010 1B68     		ldr	r3, [r3]
 828 0012 1320     		movs	r0, #19
 829 0014 9847     		blx	r3
 830              	.LVL41:
 831              	.L129:
 832              	.L132:
 833 0016 FEE7     		b	.L132
 834              	.L134:
 835              		.align	2
 836              	.L133:
 837 0018 B9010000 		.word	.LC22
 838 001c 00000000 		.word	.LANCHOR0
 839              		.cfi_endproc
 840              	.LFE18:
 842              		.section	.text.i2c0_ISR,"ax",%progbits
 843              		.align	1
 844              		.weak	i2c0_ISR
 845              		.thumb
 846              		.thumb_func
 848              	i2c0_ISR:
 849              	.LFB19:
 267:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 268:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 269:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void i2c0_ISR (void) {
 850              		.loc 1 269 0 is_stmt 1
 851              		.cfi_startproc
 852              		@ args = 0, pretend = 0, frame = 0
 853              		@ frame_needed = 0, uses_anonymous_args = 0
 854 0000 08B5     		push	{r3, lr}
 855              	.LCFI19:
 856              		.cfi_def_cfa_offset 8
 857              		.cfi_offset 3, -8
 858              		.cfi_offset 14, -4
 270:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 271:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr i2c0");
 859              		.loc 1 271 0
 860 0002 0549     		ldr	r1, .L140
 861 0004 0220     		movs	r0, #2
 862 0006 FFF7FEFF 		bl	rprintf
 863              	.LVL42:
 272:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 273:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(20);
 864              		.loc 1 273 0
 865 000a 044B     		ldr	r3, .L140+4
 866 000c 1A68     		ldr	r2, [r3]
 867 000e 12B1     		cbz	r2, .L136
 868              		.loc 1 273 0 is_stmt 0 discriminator 1
 869 0010 1B68     		ldr	r3, [r3]
 870 0012 1420     		movs	r0, #20
 871 0014 9847     		blx	r3
 872              	.LVL43:
 873              	.L136:
 874              	.L139:
 875 0016 FEE7     		b	.L139
 876              	.L141:
 877              		.align	2
 878              	.L140:
 879 0018 C4010000 		.word	.LC23
 880 001c 00000000 		.word	.LANCHOR0
 881              		.cfi_endproc
 882              	.LFE19:
 884              		.section	.text.i2c1_ISR,"ax",%progbits
 885              		.align	1
 886              		.weak	i2c1_ISR
 887              		.thumb
 888              		.thumb_func
 890              	i2c1_ISR:
 891              	.LFB20:
 274:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 275:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 276:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void i2c1_ISR (void) {
 892              		.loc 1 276 0 is_stmt 1
 893              		.cfi_startproc
 894              		@ args = 0, pretend = 0, frame = 0
 895              		@ frame_needed = 0, uses_anonymous_args = 0
 896 0000 08B5     		push	{r3, lr}
 897              	.LCFI20:
 898              		.cfi_def_cfa_offset 8
 899              		.cfi_offset 3, -8
 900              		.cfi_offset 14, -4
 277:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 278:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr i2c1");
 901              		.loc 1 278 0
 902 0002 0549     		ldr	r1, .L147
 903 0004 0220     		movs	r0, #2
 904 0006 FFF7FEFF 		bl	rprintf
 905              	.LVL44:
 279:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 280:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(21);
 906              		.loc 1 280 0
 907 000a 044B     		ldr	r3, .L147+4
 908 000c 1A68     		ldr	r2, [r3]
 909 000e 12B1     		cbz	r2, .L143
 910              		.loc 1 280 0 is_stmt 0 discriminator 1
 911 0010 1B68     		ldr	r3, [r3]
 912 0012 1520     		movs	r0, #21
 913 0014 9847     		blx	r3
 914              	.LVL45:
 915              	.L143:
 916              	.L146:
 917 0016 FEE7     		b	.L146
 918              	.L148:
 919              		.align	2
 920              	.L147:
 921 0018 D0010000 		.word	.LC24
 922 001c 00000000 		.word	.LANCHOR0
 923              		.cfi_endproc
 924              	.LFE20:
 926              		.section	.text.i2c2_ISR,"ax",%progbits
 927              		.align	1
 928              		.weak	i2c2_ISR
 929              		.thumb
 930              		.thumb_func
 932              	i2c2_ISR:
 933              	.LFB21:
 281:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 282:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 283:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void i2c2_ISR (void) {
 934              		.loc 1 283 0 is_stmt 1
 935              		.cfi_startproc
 936              		@ args = 0, pretend = 0, frame = 0
 937              		@ frame_needed = 0, uses_anonymous_args = 0
 938 0000 08B5     		push	{r3, lr}
 939              	.LCFI21:
 940              		.cfi_def_cfa_offset 8
 941              		.cfi_offset 3, -8
 942              		.cfi_offset 14, -4
 284:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 285:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr i2c2");
 943              		.loc 1 285 0
 944 0002 0549     		ldr	r1, .L154
 945 0004 0220     		movs	r0, #2
 946 0006 FFF7FEFF 		bl	rprintf
 947              	.LVL46:
 286:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 287:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(22);
 948              		.loc 1 287 0
 949 000a 044B     		ldr	r3, .L154+4
 950 000c 1A68     		ldr	r2, [r3]
 951 000e 12B1     		cbz	r2, .L150
 952              		.loc 1 287 0 is_stmt 0 discriminator 1
 953 0010 1B68     		ldr	r3, [r3]
 954 0012 1620     		movs	r0, #22
 955 0014 9847     		blx	r3
 956              	.LVL47:
 957              	.L150:
 958              	.L153:
 959 0016 FEE7     		b	.L153
 960              	.L155:
 961              		.align	2
 962              	.L154:
 963 0018 DC010000 		.word	.LC25
 964 001c 00000000 		.word	.LANCHOR0
 965              		.cfi_endproc
 966              	.LFE21:
 968              		.section	.text.spi_ISR,"ax",%progbits
 969              		.align	1
 970              		.weak	spi_ISR
 971              		.thumb
 972              		.thumb_func
 974              	spi_ISR:
 975              	.LFB22:
 288:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 289:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 290:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void spi_ISR (void) {
 976              		.loc 1 290 0 is_stmt 1
 977              		.cfi_startproc
 978              		@ args = 0, pretend = 0, frame = 0
 979              		@ frame_needed = 0, uses_anonymous_args = 0
 980 0000 08B5     		push	{r3, lr}
 981              	.LCFI22:
 982              		.cfi_def_cfa_offset 8
 983              		.cfi_offset 3, -8
 984              		.cfi_offset 14, -4
 291:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 292:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr spi");
 985              		.loc 1 292 0
 986 0002 0549     		ldr	r1, .L161
 987 0004 0220     		movs	r0, #2
 988 0006 FFF7FEFF 		bl	rprintf
 989              	.LVL48:
 293:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 294:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(23);
 990              		.loc 1 294 0
 991 000a 044B     		ldr	r3, .L161+4
 992 000c 1A68     		ldr	r2, [r3]
 993 000e 12B1     		cbz	r2, .L157
 994              		.loc 1 294 0 is_stmt 0 discriminator 1
 995 0010 1B68     		ldr	r3, [r3]
 996 0012 1720     		movs	r0, #23
 997 0014 9847     		blx	r3
 998              	.LVL49:
 999              	.L157:
 1000              	.L160:
 1001 0016 FEE7     		b	.L160
 1002              	.L162:
 1003              		.align	2
 1004              	.L161:
 1005 0018 E8010000 		.word	.LC26
 1006 001c 00000000 		.word	.LANCHOR0
 1007              		.cfi_endproc
 1008              	.LFE22:
 1010              		.section	.text.ssp0_ISR,"ax",%progbits
 1011              		.align	1
 1012              		.weak	ssp0_ISR
 1013              		.thumb
 1014              		.thumb_func
 1016              	ssp0_ISR:
 1017              	.LFB23:
 295:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 296:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 297:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void ssp0_ISR (void) {
 1018              		.loc 1 297 0 is_stmt 1
 1019              		.cfi_startproc
 1020              		@ args = 0, pretend = 0, frame = 0
 1021              		@ frame_needed = 0, uses_anonymous_args = 0
 1022 0000 08B5     		push	{r3, lr}
 1023              	.LCFI23:
 1024              		.cfi_def_cfa_offset 8
 1025              		.cfi_offset 3, -8
 1026              		.cfi_offset 14, -4
 298:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 299:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr spp0");
 1027              		.loc 1 299 0
 1028 0002 0549     		ldr	r1, .L168
 1029 0004 0220     		movs	r0, #2
 1030 0006 FFF7FEFF 		bl	rprintf
 1031              	.LVL50:
 300:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 301:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(24);
 1032              		.loc 1 301 0
 1033 000a 044B     		ldr	r3, .L168+4
 1034 000c 1A68     		ldr	r2, [r3]
 1035 000e 12B1     		cbz	r2, .L164
 1036              		.loc 1 301 0 is_stmt 0 discriminator 1
 1037 0010 1B68     		ldr	r3, [r3]
 1038 0012 1820     		movs	r0, #24
 1039 0014 9847     		blx	r3
 1040              	.LVL51:
 1041              	.L164:
 1042              	.L167:
 1043 0016 FEE7     		b	.L167
 1044              	.L169:
 1045              		.align	2
 1046              	.L168:
 1047 0018 F3010000 		.word	.LC27
 1048 001c 00000000 		.word	.LANCHOR0
 1049              		.cfi_endproc
 1050              	.LFE23:
 1052              		.section	.text.ssp1_ISR,"ax",%progbits
 1053              		.align	1
 1054              		.weak	ssp1_ISR
 1055              		.thumb
 1056              		.thumb_func
 1058              	ssp1_ISR:
 1059              	.LFB24:
 302:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 303:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 304:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void ssp1_ISR (void) {
 1060              		.loc 1 304 0 is_stmt 1
 1061              		.cfi_startproc
 1062              		@ args = 0, pretend = 0, frame = 0
 1063              		@ frame_needed = 0, uses_anonymous_args = 0
 1064 0000 08B5     		push	{r3, lr}
 1065              	.LCFI24:
 1066              		.cfi_def_cfa_offset 8
 1067              		.cfi_offset 3, -8
 1068              		.cfi_offset 14, -4
 305:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 306:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr spp1");
 1069              		.loc 1 306 0
 1070 0002 0549     		ldr	r1, .L175
 1071 0004 0220     		movs	r0, #2
 1072 0006 FFF7FEFF 		bl	rprintf
 1073              	.LVL52:
 307:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 308:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(25);
 1074              		.loc 1 308 0
 1075 000a 044B     		ldr	r3, .L175+4
 1076 000c 1A68     		ldr	r2, [r3]
 1077 000e 12B1     		cbz	r2, .L171
 1078              		.loc 1 308 0 is_stmt 0 discriminator 1
 1079 0010 1B68     		ldr	r3, [r3]
 1080 0012 1920     		movs	r0, #25
 1081 0014 9847     		blx	r3
 1082              	.LVL53:
 1083              	.L171:
 1084              	.L174:
 1085 0016 FEE7     		b	.L174
 1086              	.L176:
 1087              		.align	2
 1088              	.L175:
 1089 0018 FF010000 		.word	.LC28
 1090 001c 00000000 		.word	.LANCHOR0
 1091              		.cfi_endproc
 1092              	.LFE24:
 1094              		.section	.text.pll0_ISR,"ax",%progbits
 1095              		.align	1
 1096              		.weak	pll0_ISR
 1097              		.thumb
 1098              		.thumb_func
 1100              	pll0_ISR:
 1101              	.LFB25:
 309:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 310:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 311:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void pll0_ISR (void) {
 1102              		.loc 1 311 0 is_stmt 1
 1103              		.cfi_startproc
 1104              		@ args = 0, pretend = 0, frame = 0
 1105              		@ frame_needed = 0, uses_anonymous_args = 0
 1106 0000 08B5     		push	{r3, lr}
 1107              	.LCFI25:
 1108              		.cfi_def_cfa_offset 8
 1109              		.cfi_offset 3, -8
 1110              		.cfi_offset 14, -4
 312:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 313:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr pll0");
 1111              		.loc 1 313 0
 1112 0002 0549     		ldr	r1, .L182
 1113 0004 0220     		movs	r0, #2
 1114 0006 FFF7FEFF 		bl	rprintf
 1115              	.LVL54:
 314:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 315:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(26);
 1116              		.loc 1 315 0
 1117 000a 044B     		ldr	r3, .L182+4
 1118 000c 1A68     		ldr	r2, [r3]
 1119 000e 12B1     		cbz	r2, .L178
 1120              		.loc 1 315 0 is_stmt 0 discriminator 1
 1121 0010 1B68     		ldr	r3, [r3]
 1122 0012 1A20     		movs	r0, #26
 1123 0014 9847     		blx	r3
 1124              	.LVL55:
 1125              	.L178:
 1126              	.L181:
 1127 0016 FEE7     		b	.L181
 1128              	.L183:
 1129              		.align	2
 1130              	.L182:
 1131 0018 0B020000 		.word	.LC29
 1132 001c 00000000 		.word	.LANCHOR0
 1133              		.cfi_endproc
 1134              	.LFE25:
 1136              		.section	.text.rtc_ISR,"ax",%progbits
 1137              		.align	1
 1138              		.weak	rtc_ISR
 1139              		.thumb
 1140              		.thumb_func
 1142              	rtc_ISR:
 1143              	.LFB26:
 316:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 317:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 318:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void rtc_ISR (void) {
 1144              		.loc 1 318 0 is_stmt 1
 1145              		.cfi_startproc
 1146              		@ args = 0, pretend = 0, frame = 0
 1147              		@ frame_needed = 0, uses_anonymous_args = 0
 1148 0000 08B5     		push	{r3, lr}
 1149              	.LCFI26:
 1150              		.cfi_def_cfa_offset 8
 1151              		.cfi_offset 3, -8
 1152              		.cfi_offset 14, -4
 319:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 320:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr ");
 1153              		.loc 1 320 0
 1154 0002 0549     		ldr	r1, .L189
 1155 0004 0220     		movs	r0, #2
 1156 0006 FFF7FEFF 		bl	rprintf
 1157              	.LVL56:
 321:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 322:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(27);
 1158              		.loc 1 322 0
 1159 000a 044B     		ldr	r3, .L189+4
 1160 000c 1A68     		ldr	r2, [r3]
 1161 000e 12B1     		cbz	r2, .L185
 1162              		.loc 1 322 0 is_stmt 0 discriminator 1
 1163 0010 1B68     		ldr	r3, [r3]
 1164 0012 1B20     		movs	r0, #27
 1165 0014 9847     		blx	r3
 1166              	.LVL57:
 1167              	.L185:
 1168              	.L188:
 1169 0016 FEE7     		b	.L188
 1170              	.L190:
 1171              		.align	2
 1172              	.L189:
 1173 0018 17020000 		.word	.LC30
 1174 001c 00000000 		.word	.LANCHOR0
 1175              		.cfi_endproc
 1176              	.LFE26:
 1178              		.section	.text.eint0_ISR,"ax",%progbits
 1179              		.align	1
 1180              		.weak	eint0_ISR
 1181              		.thumb
 1182              		.thumb_func
 1184              	eint0_ISR:
 1185              	.LFB27:
 323:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 324:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 325:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void eint0_ISR (void) {
 1186              		.loc 1 325 0 is_stmt 1
 1187              		.cfi_startproc
 1188              		@ args = 0, pretend = 0, frame = 0
 1189              		@ frame_needed = 0, uses_anonymous_args = 0
 1190 0000 08B5     		push	{r3, lr}
 1191              	.LCFI27:
 1192              		.cfi_def_cfa_offset 8
 1193              		.cfi_offset 3, -8
 1194              		.cfi_offset 14, -4
 326:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** #if (VICERR_USE_DEBUG == pdON)
 327:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr eint0");
 1195              		.loc 1 327 0
 1196 0002 0549     		ldr	r1, .L196
 1197 0004 0220     		movs	r0, #2
 1198 0006 FFF7FEFF 		bl	rprintf
 1199              	.LVL58:
 328:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 329:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(28);
 1200              		.loc 1 329 0
 1201 000a 044B     		ldr	r3, .L196+4
 1202 000c 1A68     		ldr	r2, [r3]
 1203 000e 12B1     		cbz	r2, .L192
 1204              		.loc 1 329 0 is_stmt 0 discriminator 1
 1205 0010 1B68     		ldr	r3, [r3]
 1206 0012 1C20     		movs	r0, #28
 1207 0014 9847     		blx	r3
 1208              	.LVL59:
 1209              	.L192:
 1210              	.L195:
 1211 0016 FEE7     		b	.L195
 1212              	.L197:
 1213              		.align	2
 1214              	.L196:
 1215 0018 1F020000 		.word	.LC31
 1216 001c 00000000 		.word	.LANCHOR0
 1217              		.cfi_endproc
 1218              	.LFE27:
 1220              		.section	.text.eint1_ISR,"ax",%progbits
 1221              		.align	1
 1222              		.weak	eint1_ISR
 1223              		.thumb
 1224              		.thumb_func
 1226              	eint1_ISR:
 1227              	.LFB28:
 330:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 331:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 332:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void eint1_ISR (void) {
 1228              		.loc 1 332 0 is_stmt 1
 1229              		.cfi_startproc
 1230              		@ args = 0, pretend = 0, frame = 0
 1231              		@ frame_needed = 0, uses_anonymous_args = 0
 1232 0000 08B5     		push	{r3, lr}
 1233              	.LCFI28:
 1234              		.cfi_def_cfa_offset 8
 1235              		.cfi_offset 3, -8
 1236              		.cfi_offset 14, -4
 333:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 334:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr eint1");
 1237              		.loc 1 334 0
 1238 0002 0549     		ldr	r1, .L203
 1239 0004 0220     		movs	r0, #2
 1240 0006 FFF7FEFF 		bl	rprintf
 1241              	.LVL60:
 335:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 336:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(29);
 1242              		.loc 1 336 0
 1243 000a 044B     		ldr	r3, .L203+4
 1244 000c 1A68     		ldr	r2, [r3]
 1245 000e 12B1     		cbz	r2, .L199
 1246              		.loc 1 336 0 is_stmt 0 discriminator 1
 1247 0010 1B68     		ldr	r3, [r3]
 1248 0012 1D20     		movs	r0, #29
 1249 0014 9847     		blx	r3
 1250              	.LVL61:
 1251              	.L199:
 1252              	.L202:
 1253 0016 FEE7     		b	.L202
 1254              	.L204:
 1255              		.align	2
 1256              	.L203:
 1257 0018 2C020000 		.word	.LC32
 1258 001c 00000000 		.word	.LANCHOR0
 1259              		.cfi_endproc
 1260              	.LFE28:
 1262              		.section	.text.eint2_ISR,"ax",%progbits
 1263              		.align	1
 1264              		.weak	eint2_ISR
 1265              		.thumb
 1266              		.thumb_func
 1268              	eint2_ISR:
 1269              	.LFB29:
 337:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 338:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 339:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void eint2_ISR (void) {
 1270              		.loc 1 339 0 is_stmt 1
 1271              		.cfi_startproc
 1272              		@ args = 0, pretend = 0, frame = 0
 1273              		@ frame_needed = 0, uses_anonymous_args = 0
 1274 0000 08B5     		push	{r3, lr}
 1275              	.LCFI29:
 1276              		.cfi_def_cfa_offset 8
 1277              		.cfi_offset 3, -8
 1278              		.cfi_offset 14, -4
 340:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 341:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr eint2");
 1279              		.loc 1 341 0
 1280 0002 0549     		ldr	r1, .L210
 1281 0004 0220     		movs	r0, #2
 1282 0006 FFF7FEFF 		bl	rprintf
 1283              	.LVL62:
 342:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 343:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(30);
 1284              		.loc 1 343 0
 1285 000a 044B     		ldr	r3, .L210+4
 1286 000c 1A68     		ldr	r2, [r3]
 1287 000e 12B1     		cbz	r2, .L206
 1288              		.loc 1 343 0 is_stmt 0 discriminator 1
 1289 0010 1B68     		ldr	r3, [r3]
 1290 0012 1E20     		movs	r0, #30
 1291 0014 9847     		blx	r3
 1292              	.LVL63:
 1293              	.L206:
 1294              	.L209:
 1295 0016 FEE7     		b	.L209
 1296              	.L211:
 1297              		.align	2
 1298              	.L210:
 1299 0018 39020000 		.word	.LC33
 1300 001c 00000000 		.word	.LANCHOR0
 1301              		.cfi_endproc
 1302              	.LFE29:
 1304              		.section	.text.eint3_ISR,"ax",%progbits
 1305              		.align	1
 1306              		.weak	eint3_ISR
 1307              		.thumb
 1308              		.thumb_func
 1310              	eint3_ISR:
 1311              	.LFB30:
 344:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 345:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 346:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void eint3_ISR (void) {
 1312              		.loc 1 346 0 is_stmt 1
 1313              		.cfi_startproc
 1314              		@ args = 0, pretend = 0, frame = 0
 1315              		@ frame_needed = 0, uses_anonymous_args = 0
 1316 0000 08B5     		push	{r3, lr}
 1317              	.LCFI30:
 1318              		.cfi_def_cfa_offset 8
 1319              		.cfi_offset 3, -8
 1320              		.cfi_offset 14, -4
 347:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 348:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr eint3");
 1321              		.loc 1 348 0
 1322 0002 0549     		ldr	r1, .L217
 1323 0004 0220     		movs	r0, #2
 1324 0006 FFF7FEFF 		bl	rprintf
 1325              	.LVL64:
 349:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 350:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(31);
 1326              		.loc 1 350 0
 1327 000a 044B     		ldr	r3, .L217+4
 1328 000c 1A68     		ldr	r2, [r3]
 1329 000e 12B1     		cbz	r2, .L213
 1330              		.loc 1 350 0 is_stmt 0 discriminator 1
 1331 0010 1B68     		ldr	r3, [r3]
 1332 0012 1F20     		movs	r0, #31
 1333 0014 9847     		blx	r3
 1334              	.LVL65:
 1335              	.L213:
 1336              	.L216:
 1337 0016 FEE7     		b	.L216
 1338              	.L218:
 1339              		.align	2
 1340              	.L217:
 1341 0018 46020000 		.word	.LC34
 1342 001c 00000000 		.word	.LANCHOR0
 1343              		.cfi_endproc
 1344              	.LFE30:
 1346              		.section	.text.adc_ISR,"ax",%progbits
 1347              		.align	1
 1348              		.weak	adc_ISR
 1349              		.thumb
 1350              		.thumb_func
 1352              	adc_ISR:
 1353              	.LFB31:
 351:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 352:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 353:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void adc_ISR (void) {
 1354              		.loc 1 353 0 is_stmt 1
 1355              		.cfi_startproc
 1356              		@ args = 0, pretend = 0, frame = 0
 1357              		@ frame_needed = 0, uses_anonymous_args = 0
 1358 0000 08B5     		push	{r3, lr}
 1359              	.LCFI31:
 1360              		.cfi_def_cfa_offset 8
 1361              		.cfi_offset 3, -8
 1362              		.cfi_offset 14, -4
 354:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 355:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr adc");
 1363              		.loc 1 355 0
 1364 0002 0549     		ldr	r1, .L224
 1365 0004 0220     		movs	r0, #2
 1366 0006 FFF7FEFF 		bl	rprintf
 1367              	.LVL66:
 356:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 357:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(32);
 1368              		.loc 1 357 0
 1369 000a 044B     		ldr	r3, .L224+4
 1370 000c 1A68     		ldr	r2, [r3]
 1371 000e 12B1     		cbz	r2, .L220
 1372              		.loc 1 357 0 is_stmt 0 discriminator 1
 1373 0010 1B68     		ldr	r3, [r3]
 1374 0012 2020     		movs	r0, #32
 1375 0014 9847     		blx	r3
 1376              	.LVL67:
 1377              	.L220:
 1378              	.L223:
 1379 0016 FEE7     		b	.L223
 1380              	.L225:
 1381              		.align	2
 1382              	.L224:
 1383 0018 53020000 		.word	.LC35
 1384 001c 00000000 		.word	.LANCHOR0
 1385              		.cfi_endproc
 1386              	.LFE31:
 1388              		.section	.text.bod_ISR,"ax",%progbits
 1389              		.align	1
 1390              		.weak	bod_ISR
 1391              		.thumb
 1392              		.thumb_func
 1394              	bod_ISR:
 1395              	.LFB32:
 358:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 359:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 360:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void bod_ISR (void) {
 1396              		.loc 1 360 0 is_stmt 1
 1397              		.cfi_startproc
 1398              		@ args = 0, pretend = 0, frame = 0
 1399              		@ frame_needed = 0, uses_anonymous_args = 0
 1400 0000 08B5     		push	{r3, lr}
 1401              	.LCFI32:
 1402              		.cfi_def_cfa_offset 8
 1403              		.cfi_offset 3, -8
 1404              		.cfi_offset 14, -4
 361:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 362:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr bod");
 1405              		.loc 1 362 0
 1406 0002 0549     		ldr	r1, .L231
 1407 0004 0220     		movs	r0, #2
 1408 0006 FFF7FEFF 		bl	rprintf
 1409              	.LVL68:
 363:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 364:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(33);
 1410              		.loc 1 364 0
 1411 000a 044B     		ldr	r3, .L231+4
 1412 000c 1A68     		ldr	r2, [r3]
 1413 000e 12B1     		cbz	r2, .L227
 1414              		.loc 1 364 0 is_stmt 0 discriminator 1
 1415 0010 1B68     		ldr	r3, [r3]
 1416 0012 2120     		movs	r0, #33
 1417 0014 9847     		blx	r3
 1418              	.LVL69:
 1419              	.L227:
 1420              	.L230:
 1421 0016 FEE7     		b	.L230
 1422              	.L232:
 1423              		.align	2
 1424              	.L231:
 1425 0018 5E020000 		.word	.LC36
 1426 001c 00000000 		.word	.LANCHOR0
 1427              		.cfi_endproc
 1428              	.LFE32:
 1430              		.section	.text.usbHost_ISR,"ax",%progbits
 1431              		.align	1
 1432              		.weak	usbHost_ISR
 1433              		.thumb
 1434              		.thumb_func
 1436              	usbHost_ISR:
 1437              	.LFB33:
 365:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 366:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 367:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void usbHost_ISR (void) {
 1438              		.loc 1 367 0 is_stmt 1
 1439              		.cfi_startproc
 1440              		@ args = 0, pretend = 0, frame = 0
 1441              		@ frame_needed = 0, uses_anonymous_args = 0
 1442 0000 08B5     		push	{r3, lr}
 1443              	.LCFI33:
 1444              		.cfi_def_cfa_offset 8
 1445              		.cfi_offset 3, -8
 1446              		.cfi_offset 14, -4
 368:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 369:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr usb");
 1447              		.loc 1 369 0
 1448 0002 0549     		ldr	r1, .L238
 1449 0004 0220     		movs	r0, #2
 1450 0006 FFF7FEFF 		bl	rprintf
 1451              	.LVL70:
 370:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 371:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(34);
 1452              		.loc 1 371 0
 1453 000a 044B     		ldr	r3, .L238+4
 1454 000c 1A68     		ldr	r2, [r3]
 1455 000e 12B1     		cbz	r2, .L234
 1456              		.loc 1 371 0 is_stmt 0 discriminator 1
 1457 0010 1B68     		ldr	r3, [r3]
 1458 0012 2220     		movs	r0, #34
 1459 0014 9847     		blx	r3
 1460              	.LVL71:
 1461              	.L234:
 1462              	.L237:
 1463 0016 FEE7     		b	.L237
 1464              	.L239:
 1465              		.align	2
 1466              	.L238:
 1467 0018 69020000 		.word	.LC37
 1468 001c 00000000 		.word	.LANCHOR0
 1469              		.cfi_endproc
 1470              	.LFE33:
 1472              		.section	.text.can_ISR,"ax",%progbits
 1473              		.align	1
 1474              		.weak	can_ISR
 1475              		.thumb
 1476              		.thumb_func
 1478              	can_ISR:
 1479              	.LFB34:
 372:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 373:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 374:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void can_ISR (void) {
 1480              		.loc 1 374 0 is_stmt 1
 1481              		.cfi_startproc
 1482              		@ args = 0, pretend = 0, frame = 0
 1483              		@ frame_needed = 0, uses_anonymous_args = 0
 1484 0000 08B5     		push	{r3, lr}
 1485              	.LCFI34:
 1486              		.cfi_def_cfa_offset 8
 1487              		.cfi_offset 3, -8
 1488              		.cfi_offset 14, -4
 375:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 376:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr can");
 1489              		.loc 1 376 0
 1490 0002 0549     		ldr	r1, .L245
 1491 0004 0220     		movs	r0, #2
 1492 0006 FFF7FEFF 		bl	rprintf
 1493              	.LVL72:
 377:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 378:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(35);
 1494              		.loc 1 378 0
 1495 000a 044B     		ldr	r3, .L245+4
 1496 000c 1A68     		ldr	r2, [r3]
 1497 000e 12B1     		cbz	r2, .L241
 1498              		.loc 1 378 0 is_stmt 0 discriminator 1
 1499 0010 1B68     		ldr	r3, [r3]
 1500 0012 2320     		movs	r0, #35
 1501 0014 9847     		blx	r3
 1502              	.LVL73:
 1503              	.L241:
 1504              	.L244:
 1505 0016 FEE7     		b	.L244
 1506              	.L246:
 1507              		.align	2
 1508              	.L245:
 1509 0018 74020000 		.word	.LC38
 1510 001c 00000000 		.word	.LANCHOR0
 1511              		.cfi_endproc
 1512              	.LFE34:
 1514              		.section	.text.dma_ISR,"ax",%progbits
 1515              		.align	1
 1516              		.weak	dma_ISR
 1517              		.thumb
 1518              		.thumb_func
 1520              	dma_ISR:
 1521              	.LFB35:
 379:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 380:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 381:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void dma_ISR (void) {
 1522              		.loc 1 381 0 is_stmt 1
 1523              		.cfi_startproc
 1524              		@ args = 0, pretend = 0, frame = 0
 1525              		@ frame_needed = 0, uses_anonymous_args = 0
 1526 0000 08B5     		push	{r3, lr}
 1527              	.LCFI35:
 1528              		.cfi_def_cfa_offset 8
 1529              		.cfi_offset 3, -8
 1530              		.cfi_offset 14, -4
 382:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 383:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr dma");
 1531              		.loc 1 383 0
 1532 0002 0549     		ldr	r1, .L252
 1533 0004 0220     		movs	r0, #2
 1534 0006 FFF7FEFF 		bl	rprintf
 1535              	.LVL74:
 384:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 385:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(36);
 1536              		.loc 1 385 0
 1537 000a 044B     		ldr	r3, .L252+4
 1538 000c 1A68     		ldr	r2, [r3]
 1539 000e 12B1     		cbz	r2, .L248
 1540              		.loc 1 385 0 is_stmt 0 discriminator 1
 1541 0010 1B68     		ldr	r3, [r3]
 1542 0012 2420     		movs	r0, #36
 1543 0014 9847     		blx	r3
 1544              	.LVL75:
 1545              	.L248:
 1546              	.L251:
 1547 0016 FEE7     		b	.L251
 1548              	.L253:
 1549              		.align	2
 1550              	.L252:
 1551 0018 7F020000 		.word	.LC39
 1552 001c 00000000 		.word	.LANCHOR0
 1553              		.cfi_endproc
 1554              	.LFE35:
 1556              		.section	.text.i2s_ISR,"ax",%progbits
 1557              		.align	1
 1558              		.weak	i2s_ISR
 1559              		.thumb
 1560              		.thumb_func
 1562              	i2s_ISR:
 1563              	.LFB36:
 386:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 387:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 388:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void i2s_ISR (void) {
 1564              		.loc 1 388 0 is_stmt 1
 1565              		.cfi_startproc
 1566              		@ args = 0, pretend = 0, frame = 0
 1567              		@ frame_needed = 0, uses_anonymous_args = 0
 1568 0000 08B5     		push	{r3, lr}
 1569              	.LCFI36:
 1570              		.cfi_def_cfa_offset 8
 1571              		.cfi_offset 3, -8
 1572              		.cfi_offset 14, -4
 389:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 390:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr i2s");
 1573              		.loc 1 390 0
 1574 0002 0549     		ldr	r1, .L259
 1575 0004 0220     		movs	r0, #2
 1576 0006 FFF7FEFF 		bl	rprintf
 1577              	.LVL76:
 391:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 392:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(37);
 1578              		.loc 1 392 0
 1579 000a 044B     		ldr	r3, .L259+4
 1580 000c 1A68     		ldr	r2, [r3]
 1581 000e 12B1     		cbz	r2, .L255
 1582              		.loc 1 392 0 is_stmt 0 discriminator 1
 1583 0010 1B68     		ldr	r3, [r3]
 1584 0012 2520     		movs	r0, #37
 1585 0014 9847     		blx	r3
 1586              	.LVL77:
 1587              	.L255:
 1588              	.L258:
 1589 0016 FEE7     		b	.L258
 1590              	.L260:
 1591              		.align	2
 1592              	.L259:
 1593 0018 8A020000 		.word	.LC40
 1594 001c 00000000 		.word	.LANCHOR0
 1595              		.cfi_endproc
 1596              	.LFE36:
 1598              		.section	.text.enet_ISR,"ax",%progbits
 1599              		.align	1
 1600              		.weak	enet_ISR
 1601              		.thumb
 1602              		.thumb_func
 1604              	enet_ISR:
 1605              	.LFB37:
 393:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 394:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 395:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void enet_ISR (void) {
 1606              		.loc 1 395 0 is_stmt 1
 1607              		.cfi_startproc
 1608              		@ args = 0, pretend = 0, frame = 0
 1609              		@ frame_needed = 0, uses_anonymous_args = 0
 1610 0000 08B5     		push	{r3, lr}
 1611              	.LCFI37:
 1612              		.cfi_def_cfa_offset 8
 1613              		.cfi_offset 3, -8
 1614              		.cfi_offset 14, -4
 396:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 397:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr enet");
 1615              		.loc 1 397 0
 1616 0002 0549     		ldr	r1, .L266
 1617 0004 0220     		movs	r0, #2
 1618 0006 FFF7FEFF 		bl	rprintf
 1619              	.LVL78:
 398:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 399:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(38);
 1620              		.loc 1 399 0
 1621 000a 044B     		ldr	r3, .L266+4
 1622 000c 1A68     		ldr	r2, [r3]
 1623 000e 12B1     		cbz	r2, .L262
 1624              		.loc 1 399 0 is_stmt 0 discriminator 1
 1625 0010 1B68     		ldr	r3, [r3]
 1626 0012 2620     		movs	r0, #38
 1627 0014 9847     		blx	r3
 1628              	.LVL79:
 1629              	.L262:
 1630              	.L265:
 1631 0016 FEE7     		b	.L265
 1632              	.L267:
 1633              		.align	2
 1634              	.L266:
 1635 0018 95020000 		.word	.LC41
 1636 001c 00000000 		.word	.LANCHOR0
 1637              		.cfi_endproc
 1638              	.LFE37:
 1640              		.section	.text.rit_ISR,"ax",%progbits
 1641              		.align	1
 1642              		.weak	rit_ISR
 1643              		.thumb
 1644              		.thumb_func
 1646              	rit_ISR:
 1647              	.LFB38:
 400:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 401:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 402:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void rit_ISR (void) {
 1648              		.loc 1 402 0 is_stmt 1
 1649              		.cfi_startproc
 1650              		@ args = 0, pretend = 0, frame = 0
 1651              		@ frame_needed = 0, uses_anonymous_args = 0
 1652 0000 08B5     		push	{r3, lr}
 1653              	.LCFI38:
 1654              		.cfi_def_cfa_offset 8
 1655              		.cfi_offset 3, -8
 1656              		.cfi_offset 14, -4
 403:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 404:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr rit");
 1657              		.loc 1 404 0
 1658 0002 0549     		ldr	r1, .L273
 1659 0004 0220     		movs	r0, #2
 1660 0006 FFF7FEFF 		bl	rprintf
 1661              	.LVL80:
 405:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 406:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(39);
 1662              		.loc 1 406 0
 1663 000a 044B     		ldr	r3, .L273+4
 1664 000c 1A68     		ldr	r2, [r3]
 1665 000e 12B1     		cbz	r2, .L269
 1666              		.loc 1 406 0 is_stmt 0 discriminator 1
 1667 0010 1B68     		ldr	r3, [r3]
 1668 0012 2720     		movs	r0, #39
 1669 0014 9847     		blx	r3
 1670              	.LVL81:
 1671              	.L269:
 1672              	.L272:
 1673 0016 FEE7     		b	.L272
 1674              	.L274:
 1675              		.align	2
 1676              	.L273:
 1677 0018 A1020000 		.word	.LC42
 1678 001c 00000000 		.word	.LANCHOR0
 1679              		.cfi_endproc
 1680              	.LFE38:
 1682              		.section	.text.mcpwm_ISR,"ax",%progbits
 1683              		.align	1
 1684              		.weak	mcpwm_ISR
 1685              		.thumb
 1686              		.thumb_func
 1688              	mcpwm_ISR:
 1689              	.LFB39:
 407:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 408:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 409:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void mcpwm_ISR (void) {
 1690              		.loc 1 409 0 is_stmt 1
 1691              		.cfi_startproc
 1692              		@ args = 0, pretend = 0, frame = 0
 1693              		@ frame_needed = 0, uses_anonymous_args = 0
 1694 0000 08B5     		push	{r3, lr}
 1695              	.LCFI39:
 1696              		.cfi_def_cfa_offset 8
 1697              		.cfi_offset 3, -8
 1698              		.cfi_offset 14, -4
 410:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 411:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr mcpwm");
 1699              		.loc 1 411 0
 1700 0002 0549     		ldr	r1, .L280
 1701 0004 0220     		movs	r0, #2
 1702 0006 FFF7FEFF 		bl	rprintf
 1703              	.LVL82:
 412:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 413:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(40);
 1704              		.loc 1 413 0
 1705 000a 044B     		ldr	r3, .L280+4
 1706 000c 1A68     		ldr	r2, [r3]
 1707 000e 12B1     		cbz	r2, .L276
 1708              		.loc 1 413 0 is_stmt 0 discriminator 1
 1709 0010 1B68     		ldr	r3, [r3]
 1710 0012 2820     		movs	r0, #40
 1711 0014 9847     		blx	r3
 1712              	.LVL83:
 1713              	.L276:
 1714              	.L279:
 1715 0016 FEE7     		b	.L279
 1716              	.L281:
 1717              		.align	2
 1718              	.L280:
 1719 0018 AC020000 		.word	.LC43
 1720 001c 00000000 		.word	.LANCHOR0
 1721              		.cfi_endproc
 1722              	.LFE39:
 1724              		.section	.text.qei_ISR,"ax",%progbits
 1725              		.align	1
 1726              		.weak	qei_ISR
 1727              		.thumb
 1728              		.thumb_func
 1730              	qei_ISR:
 1731              	.LFB40:
 414:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 415:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 416:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void qei_ISR (void) {
 1732              		.loc 1 416 0 is_stmt 1
 1733              		.cfi_startproc
 1734              		@ args = 0, pretend = 0, frame = 0
 1735              		@ frame_needed = 0, uses_anonymous_args = 0
 1736 0000 08B5     		push	{r3, lr}
 1737              	.LCFI40:
 1738              		.cfi_def_cfa_offset 8
 1739              		.cfi_offset 3, -8
 1740              		.cfi_offset 14, -4
 417:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 418:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr qei");
 1741              		.loc 1 418 0
 1742 0002 0549     		ldr	r1, .L287
 1743 0004 0220     		movs	r0, #2
 1744 0006 FFF7FEFF 		bl	rprintf
 1745              	.LVL84:
 419:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 420:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(41);
 1746              		.loc 1 420 0
 1747 000a 044B     		ldr	r3, .L287+4
 1748 000c 1A68     		ldr	r2, [r3]
 1749 000e 12B1     		cbz	r2, .L283
 1750              		.loc 1 420 0 is_stmt 0 discriminator 1
 1751 0010 1B68     		ldr	r3, [r3]
 1752 0012 2920     		movs	r0, #41
 1753 0014 9847     		blx	r3
 1754              	.LVL85:
 1755              	.L283:
 1756              	.L286:
 1757 0016 FEE7     		b	.L286
 1758              	.L288:
 1759              		.align	2
 1760              	.L287:
 1761 0018 B9020000 		.word	.LC44
 1762 001c 00000000 		.word	.LANCHOR0
 1763              		.cfi_endproc
 1764              	.LFE40:
 1766              		.section	.text.pll1_ISR,"ax",%progbits
 1767              		.align	1
 1768              		.weak	pll1_ISR
 1769              		.thumb
 1770              		.thumb_func
 1772              	pll1_ISR:
 1773              	.LFB41:
 421:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 422:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 423:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 424:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void pll1_ISR (void) {
 1774              		.loc 1 424 0 is_stmt 1
 1775              		.cfi_startproc
 1776              		@ args = 0, pretend = 0, frame = 0
 1777              		@ frame_needed = 0, uses_anonymous_args = 0
 1778 0000 08B5     		push	{r3, lr}
 1779              	.LCFI41:
 1780              		.cfi_def_cfa_offset 8
 1781              		.cfi_offset 3, -8
 1782              		.cfi_offset 14, -4
 425:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 426:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr pll1");
 1783              		.loc 1 426 0
 1784 0002 0549     		ldr	r1, .L294
 1785 0004 0220     		movs	r0, #2
 1786 0006 FFF7FEFF 		bl	rprintf
 1787              	.LVL86:
 427:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 428:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(42);
 1788              		.loc 1 428 0
 1789 000a 044B     		ldr	r3, .L294+4
 1790 000c 1A68     		ldr	r2, [r3]
 1791 000e 12B1     		cbz	r2, .L290
 1792              		.loc 1 428 0 is_stmt 0 discriminator 1
 1793 0010 1B68     		ldr	r3, [r3]
 1794 0012 2A20     		movs	r0, #42
 1795 0014 9847     		blx	r3
 1796              	.LVL87:
 1797              	.L290:
 1798              	.L293:
 1799 0016 FEE7     		b	.L293
 1800              	.L295:
 1801              		.align	2
 1802              	.L294:
 1803 0018 C4020000 		.word	.LC45
 1804 001c 00000000 		.word	.LANCHOR0
 1805              		.cfi_endproc
 1806              	.LFE41:
 1808              		.section	.text.usbAct_ISR,"ax",%progbits
 1809              		.align	1
 1810              		.weak	usbAct_ISR
 1811              		.thumb
 1812              		.thumb_func
 1814              	usbAct_ISR:
 1815              	.LFB42:
 429:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 430:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 431:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 432:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void usbAct_ISR (void) {
 1816              		.loc 1 432 0 is_stmt 1
 1817              		.cfi_startproc
 1818              		@ args = 0, pretend = 0, frame = 0
 1819              		@ frame_needed = 0, uses_anonymous_args = 0
 1820 0000 08B5     		push	{r3, lr}
 1821              	.LCFI42:
 1822              		.cfi_def_cfa_offset 8
 1823              		.cfi_offset 3, -8
 1824              		.cfi_offset 14, -4
 433:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 434:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr USB ACT");
 1825              		.loc 1 434 0
 1826 0002 0549     		ldr	r1, .L301
 1827 0004 0220     		movs	r0, #2
 1828 0006 FFF7FEFF 		bl	rprintf
 1829              	.LVL88:
 435:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 436:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(43);
 1830              		.loc 1 436 0
 1831 000a 044B     		ldr	r3, .L301+4
 1832 000c 1A68     		ldr	r2, [r3]
 1833 000e 12B1     		cbz	r2, .L297
 1834              		.loc 1 436 0 is_stmt 0 discriminator 1
 1835 0010 1B68     		ldr	r3, [r3]
 1836 0012 2B20     		movs	r0, #43
 1837 0014 9847     		blx	r3
 1838              	.LVL89:
 1839              	.L297:
 1840              	.L300:
 1841 0016 FEE7     		b	.L300
 1842              	.L302:
 1843              		.align	2
 1844              	.L301:
 1845 0018 D0020000 		.word	.LC46
 1846 001c 00000000 		.word	.LANCHOR0
 1847              		.cfi_endproc
 1848              	.LFE42:
 1850              		.section	.text.canAct_ISR,"ax",%progbits
 1851              		.align	1
 1852              		.weak	canAct_ISR
 1853              		.thumb
 1854              		.thumb_func
 1856              	canAct_ISR:
 1857              	.LFB43:
 437:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 438:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 439:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void canAct_ISR (void) {
 1858              		.loc 1 439 0 is_stmt 1
 1859              		.cfi_startproc
 1860              		@ args = 0, pretend = 0, frame = 0
 1861              		@ frame_needed = 0, uses_anonymous_args = 0
 1862 0000 08B5     		push	{r3, lr}
 1863              	.LCFI43:
 1864              		.cfi_def_cfa_offset 8
 1865              		.cfi_offset 3, -8
 1866              		.cfi_offset 14, -4
 440:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 441:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr CAN ACT");
 1867              		.loc 1 441 0
 1868 0002 0549     		ldr	r1, .L308
 1869 0004 0220     		movs	r0, #2
 1870 0006 FFF7FEFF 		bl	rprintf
 1871              	.LVL90:
 442:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 443:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(44);
 1872              		.loc 1 443 0
 1873 000a 044B     		ldr	r3, .L308+4
 1874 000c 1A68     		ldr	r2, [r3]
 1875 000e 12B1     		cbz	r2, .L304
 1876              		.loc 1 443 0 is_stmt 0 discriminator 1
 1877 0010 1B68     		ldr	r3, [r3]
 1878 0012 2C20     		movs	r0, #44
 1879 0014 9847     		blx	r3
 1880              	.LVL91:
 1881              	.L304:
 1882              	.L307:
 1883 0016 FEE7     		b	.L307
 1884              	.L309:
 1885              		.align	2
 1886              	.L308:
 1887 0018 DF020000 		.word	.LC47
 1888 001c 00000000 		.word	.LANCHOR0
 1889              		.cfi_endproc
 1890              	.LFE43:
 1892              		.section	.text.uart4_ISR,"ax",%progbits
 1893              		.align	1
 1894              		.weak	uart4_ISR
 1895              		.thumb
 1896              		.thumb_func
 1898              	uart4_ISR:
 1899              	.LFB44:
 444:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 445:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 446:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void uart4_ISR (void) {
 1900              		.loc 1 446 0 is_stmt 1
 1901              		.cfi_startproc
 1902              		@ args = 0, pretend = 0, frame = 0
 1903              		@ frame_needed = 0, uses_anonymous_args = 0
 1904 0000 08B5     		push	{r3, lr}
 1905              	.LCFI44:
 1906              		.cfi_def_cfa_offset 8
 1907              		.cfi_offset 3, -8
 1908              		.cfi_offset 14, -4
 447:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 448:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr uart4");
 1909              		.loc 1 448 0
 1910 0002 0549     		ldr	r1, .L315
 1911 0004 0220     		movs	r0, #2
 1912 0006 FFF7FEFF 		bl	rprintf
 1913              	.LVL92:
 449:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 450:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(45);
 1914              		.loc 1 450 0
 1915 000a 044B     		ldr	r3, .L315+4
 1916 000c 1A68     		ldr	r2, [r3]
 1917 000e 12B1     		cbz	r2, .L311
 1918              		.loc 1 450 0 is_stmt 0 discriminator 1
 1919 0010 1B68     		ldr	r3, [r3]
 1920 0012 2D20     		movs	r0, #45
 1921 0014 9847     		blx	r3
 1922              	.LVL93:
 1923              	.L311:
 1924              	.L314:
 1925 0016 FEE7     		b	.L314
 1926              	.L316:
 1927              		.align	2
 1928              	.L315:
 1929 0018 EE020000 		.word	.LC48
 1930 001c 00000000 		.word	.LANCHOR0
 1931              		.cfi_endproc
 1932              	.LFE44:
 1934              		.section	.text.ssp2_ISR,"ax",%progbits
 1935              		.align	1
 1936              		.weak	ssp2_ISR
 1937              		.thumb
 1938              		.thumb_func
 1940              	ssp2_ISR:
 1941              	.LFB45:
 451:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 452:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 453:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void ssp2_ISR (void) {
 1942              		.loc 1 453 0 is_stmt 1
 1943              		.cfi_startproc
 1944              		@ args = 0, pretend = 0, frame = 0
 1945              		@ frame_needed = 0, uses_anonymous_args = 0
 1946 0000 08B5     		push	{r3, lr}
 1947              	.LCFI45:
 1948              		.cfi_def_cfa_offset 8
 1949              		.cfi_offset 3, -8
 1950              		.cfi_offset 14, -4
 454:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 455:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr ssp2");
 1951              		.loc 1 455 0
 1952 0002 0549     		ldr	r1, .L322
 1953 0004 0220     		movs	r0, #2
 1954 0006 FFF7FEFF 		bl	rprintf
 1955              	.LVL94:
 456:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 457:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(46);
 1956              		.loc 1 457 0
 1957 000a 044B     		ldr	r3, .L322+4
 1958 000c 1A68     		ldr	r2, [r3]
 1959 000e 12B1     		cbz	r2, .L318
 1960              		.loc 1 457 0 is_stmt 0 discriminator 1
 1961 0010 1B68     		ldr	r3, [r3]
 1962 0012 2E20     		movs	r0, #46
 1963 0014 9847     		blx	r3
 1964              	.LVL95:
 1965              	.L318:
 1966              	.L321:
 1967 0016 FEE7     		b	.L321
 1968              	.L323:
 1969              		.align	2
 1970              	.L322:
 1971 0018 FB020000 		.word	.LC49
 1972 001c 00000000 		.word	.LANCHOR0
 1973              		.cfi_endproc
 1974              	.LFE45:
 1976              		.section	.text.lcd_ISR,"ax",%progbits
 1977              		.align	1
 1978              		.weak	lcd_ISR
 1979              		.thumb
 1980              		.thumb_func
 1982              	lcd_ISR:
 1983              	.LFB46:
 458:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 459:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 460:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void lcd_ISR (void) {
 1984              		.loc 1 460 0 is_stmt 1
 1985              		.cfi_startproc
 1986              		@ args = 0, pretend = 0, frame = 0
 1987              		@ frame_needed = 0, uses_anonymous_args = 0
 1988 0000 08B5     		push	{r3, lr}
 1989              	.LCFI46:
 1990              		.cfi_def_cfa_offset 8
 1991              		.cfi_offset 3, -8
 1992              		.cfi_offset 14, -4
 461:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 462:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr lcd");
 1993              		.loc 1 462 0
 1994 0002 0549     		ldr	r1, .L329
 1995 0004 0220     		movs	r0, #2
 1996 0006 FFF7FEFF 		bl	rprintf
 1997              	.LVL96:
 463:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 464:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(47);
 1998              		.loc 1 464 0
 1999 000a 044B     		ldr	r3, .L329+4
 2000 000c 1A68     		ldr	r2, [r3]
 2001 000e 12B1     		cbz	r2, .L325
 2002              		.loc 1 464 0 is_stmt 0 discriminator 1
 2003 0010 1B68     		ldr	r3, [r3]
 2004 0012 2F20     		movs	r0, #47
 2005 0014 9847     		blx	r3
 2006              	.LVL97:
 2007              	.L325:
 2008              	.L328:
 2009 0016 FEE7     		b	.L328
 2010              	.L330:
 2011              		.align	2
 2012              	.L329:
 2013 0018 07030000 		.word	.LC50
 2014 001c 00000000 		.word	.LANCHOR0
 2015              		.cfi_endproc
 2016              	.LFE46:
 2018              		.section	.text.gpio_ISR,"ax",%progbits
 2019              		.align	1
 2020              		.weak	gpio_ISR
 2021              		.thumb
 2022              		.thumb_func
 2024              	gpio_ISR:
 2025              	.LFB47:
 465:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 466:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 467:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void gpio_ISR (void) {
 2026              		.loc 1 467 0 is_stmt 1
 2027              		.cfi_startproc
 2028              		@ args = 0, pretend = 0, frame = 0
 2029              		@ frame_needed = 0, uses_anonymous_args = 0
 2030 0000 08B5     		push	{r3, lr}
 2031              	.LCFI47:
 2032              		.cfi_def_cfa_offset 8
 2033              		.cfi_offset 3, -8
 2034              		.cfi_offset 14, -4
 468:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 469:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr gpio");
 2035              		.loc 1 469 0
 2036 0002 0549     		ldr	r1, .L336
 2037 0004 0220     		movs	r0, #2
 2038 0006 FFF7FEFF 		bl	rprintf
 2039              	.LVL98:
 470:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 471:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(48);
 2040              		.loc 1 471 0
 2041 000a 044B     		ldr	r3, .L336+4
 2042 000c 1A68     		ldr	r2, [r3]
 2043 000e 12B1     		cbz	r2, .L332
 2044              		.loc 1 471 0 is_stmt 0 discriminator 1
 2045 0010 1B68     		ldr	r3, [r3]
 2046 0012 3020     		movs	r0, #48
 2047 0014 9847     		blx	r3
 2048              	.LVL99:
 2049              	.L332:
 2050              	.L335:
 2051 0016 FEE7     		b	.L335
 2052              	.L337:
 2053              		.align	2
 2054              	.L336:
 2055 0018 12030000 		.word	.LC51
 2056 001c 00000000 		.word	.LANCHOR0
 2057              		.cfi_endproc
 2058              	.LFE47:
 2060              		.section	.text.pwm0_ISR,"ax",%progbits
 2061              		.align	1
 2062              		.weak	pwm0_ISR
 2063              		.thumb
 2064              		.thumb_func
 2066              	pwm0_ISR:
 2067              	.LFB48:
 472:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 473:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 474:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void pwm0_ISR (void) {
 2068              		.loc 1 474 0 is_stmt 1
 2069              		.cfi_startproc
 2070              		@ args = 0, pretend = 0, frame = 0
 2071              		@ frame_needed = 0, uses_anonymous_args = 0
 2072 0000 08B5     		push	{r3, lr}
 2073              	.LCFI48:
 2074              		.cfi_def_cfa_offset 8
 2075              		.cfi_offset 3, -8
 2076              		.cfi_offset 14, -4
 475:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 476:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr pwm0");
 2077              		.loc 1 476 0
 2078 0002 0549     		ldr	r1, .L343
 2079 0004 0220     		movs	r0, #2
 2080 0006 FFF7FEFF 		bl	rprintf
 2081              	.LVL100:
 477:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 478:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(49);
 2082              		.loc 1 478 0
 2083 000a 044B     		ldr	r3, .L343+4
 2084 000c 1A68     		ldr	r2, [r3]
 2085 000e 12B1     		cbz	r2, .L339
 2086              		.loc 1 478 0 is_stmt 0 discriminator 1
 2087 0010 1B68     		ldr	r3, [r3]
 2088 0012 3120     		movs	r0, #49
 2089 0014 9847     		blx	r3
 2090              	.LVL101:
 2091              	.L339:
 2092              	.L342:
 2093 0016 FEE7     		b	.L342
 2094              	.L344:
 2095              		.align	2
 2096              	.L343:
 2097 0018 1E030000 		.word	.LC52
 2098 001c 00000000 		.word	.LANCHOR0
 2099              		.cfi_endproc
 2100              	.LFE48:
 2102              		.section	.text.eeprom_ISR,"ax",%progbits
 2103              		.align	1
 2104              		.weak	eeprom_ISR
 2105              		.thumb
 2106              		.thumb_func
 2108              	eeprom_ISR:
 2109              	.LFB49:
 479:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 480:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 481:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void eeprom_ISR (void) {
 2110              		.loc 1 481 0 is_stmt 1
 2111              		.cfi_startproc
 2112              		@ args = 0, pretend = 0, frame = 0
 2113              		@ frame_needed = 0, uses_anonymous_args = 0
 2114 0000 08B5     		push	{r3, lr}
 2115              	.LCFI49:
 2116              		.cfi_def_cfa_offset 8
 2117              		.cfi_offset 3, -8
 2118              		.cfi_offset 14, -4
 482:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VICERR_USE_DEBUG == pdON)
 483:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("vicErr eeprom");
 2119              		.loc 1 483 0
 2120 0002 0549     		ldr	r1, .L350
 2121 0004 0220     		movs	r0, #2
 2122 0006 FFF7FEFF 		bl	rprintf
 2123              	.LVL102:
 484:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 485:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if (vicerr_Functions) vicerr_Functions(50);
 2124              		.loc 1 485 0
 2125 000a 044B     		ldr	r3, .L350+4
 2126 000c 1A68     		ldr	r2, [r3]
 2127 000e 12B1     		cbz	r2, .L346
 2128              		.loc 1 485 0 is_stmt 0 discriminator 1
 2129 0010 1B68     		ldr	r3, [r3]
 2130 0012 3220     		movs	r0, #50
 2131 0014 9847     		blx	r3
 2132              	.LVL103:
 2133              	.L346:
 2134              	.L349:
 2135 0016 FEE7     		b	.L349
 2136              	.L351:
 2137              		.align	2
 2138              	.L350:
 2139 0018 2A030000 		.word	.LC53
 2140 001c 00000000 		.word	.LANCHOR0
 2141              		.cfi_endproc
 2142              	.LFE49:
 2144              		.section	.text.nvic_disableIRQ,"ax",%progbits
 2145              		.align	1
 2146              		.global	nvic_disableIRQ
 2147              		.thumb
 2148              		.thumb_func
 2150              	nvic_disableIRQ:
 2151              	.LFB51:
 486:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	while(1);
 487:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 488:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 489:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 490:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Descrição:	Habilita a interrupção de um determinado periférico
 491:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Parametro:	ID da interrupção do periférico
 492:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Retorna:		Nada
 493:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 494:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void nvic_enableIRQ(u8 numIRQ) {
 495:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VIC_USE_DEBUG == pdON)
 496:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("enableIRQ [%u][%u]"CMD_TERMINATOR, numIRQ, (u32)numIRQ/VIC_SIZE);
 497:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 498:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	reg32 *addrPort = &ISER0; 		// Pegar o endereço do registrador para habilitar a int
 499:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VIC_USE_DEBUG == pdON)
 500:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("addrPort 0x%x"CMD_TERMINATOR, addrPort);
 501:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 502:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 503:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	addrPort+=(reg32)(numIRQ/VIC_SIZE); 	// Determinar em que registrador pertence ao periférico
 504:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VIC_USE_DEBUG == pdON)
 505:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("addrPort 0x%x = 0x%x "CMD_TERMINATOR, addrPort, (1 << (numIRQ%VIC_SIZE)));
 506:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 507:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	*addrPort = (1 << (numIRQ%VIC_SIZE));	// Habilitar interrupção do periférico
 508:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 509:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 510:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 511:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Descrição:	Desabilita a interrupção de um determinado periférico
 512:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Parametro:	ID da interrupção do periférico
 513:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Retorna:		Nada
 514:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 515:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void nvic_disableIRQ(u8 numIRQ) {
 2152              		.loc 1 515 0 is_stmt 1
 2153              		.cfi_startproc
 2154              		@ args = 0, pretend = 0, frame = 0
 2155              		@ frame_needed = 0, uses_anonymous_args = 0
 2156              		@ link register save eliminated.
 2157              	.LVL104:
 516:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	reg32 *addrPort = &ICER0; 		// Pegar o endereço do registrador do periférico
 517:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	addrPort+=(reg32)(numIRQ/VIC_SIZE); 	// Determinar em que registrador pertence ao periférico
 2158              		.loc 1 517 0
 2159 0000 4209     		lsrs	r2, r0, #5
 2160              	.LVL105:
 518:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	*addrPort = (1 << (numIRQ%VIC_SIZE));	// Desabilitar a  interrupção do periférico
 2161              		.loc 1 518 0
 2162 0002 0123     		movs	r3, #1
 2163 0004 00F01F00 		and	r0, r0, #31
 2164              	.LVL106:
 2165 0008 03FA00F0 		lsl	r0, r3, r0
 2166 000c 014B     		ldr	r3, .L353
 2167 000e 43F82200 		str	r0, [r3, r2, lsl #2]
 2168 0012 7047     		bx	lr
 2169              	.L354:
 2170              		.align	2
 2171              	.L353:
 2172 0014 80E100E0 		.word	-536813184
 2173              		.cfi_endproc
 2174              	.LFE51:
 2176              		.section	.text.nvic_getPendingIRQ,"ax",%progbits
 2177              		.align	1
 2178              		.global	nvic_getPendingIRQ
 2179              		.thumb
 2180              		.thumb_func
 2182              	nvic_getPendingIRQ:
 2183              	.LFB52:
 519:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 520:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 521:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 522:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Descrição:	Verifica se o a interrupção de um determinado periférico está pendente ou não
 523:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Parametro:	ID da interrupção do periférico
 524:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Retorna:		Retorna pdTRUE e a interrupção do periférico está pendente, senão pdFALSE
 525:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 526:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** u8 nvic_getPendingIRQ(u8 numIRQ) {
 2184              		.loc 1 526 0
 2185              		.cfi_startproc
 2186              		@ args = 0, pretend = 0, frame = 0
 2187              		@ frame_needed = 0, uses_anonymous_args = 0
 2188              		@ link register save eliminated.
 2189              	.LVL107:
 527:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	reg32 *addrPort = &ISER0; 			// Pegar o endereço do registrador do periférico
 528:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	addrPort+=(reg32)(numIRQ/VIC_SIZE); // Determinar em que registrador pertence ao periférico
 2190              		.loc 1 528 0
 2191 0000 4309     		lsrs	r3, r0, #5
 2192 0002 9B00     		lsls	r3, r3, #2
 2193 0004 03F16043 		add	r3, r3, #-536870912
 2194 0008 03F56143 		add	r3, r3, #57600
 2195              	.LVL108:
 529:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	return ( *addrPort & (1 << (numIRQ%VIC_SIZE)) )?pdTRUE:pdFALSE;
 2196              		.loc 1 529 0
 2197 000c 1A68     		ldr	r2, [r3]
 2198 000e 00F01F00 		and	r0, r0, #31
 2199              	.LVL109:
 2200 0012 0123     		movs	r3, #1
 2201              	.LVL110:
 2202 0014 03FA00F0 		lsl	r0, r3, r0
 2203 0018 1042     		tst	r0, r2
 530:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 2204              		.loc 1 530 0
 2205 001a 14BF     		ite	ne
 2206 001c 1846     		movne	r0, r3
 2207 001e 0020     		moveq	r0, #0
 2208 0020 7047     		bx	lr
 2209              		.cfi_endproc
 2210              	.LFE52:
 2212              		.section	.text.nvic_setPendingIRQ,"ax",%progbits
 2213              		.align	1
 2214              		.global	nvic_setPendingIRQ
 2215              		.thumb
 2216              		.thumb_func
 2218              	nvic_setPendingIRQ:
 2219              	.LFB53:
 531:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 532:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 533:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Descrição:	Habilita a pendencia da interrupção de um determinado periférico
 534:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Parametro:	ID da interrupção do periférico
 535:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Retorna:		Nada
 536:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 537:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void nvic_setPendingIRQ(u8 numIRQ) {
 2220              		.loc 1 537 0
 2221              		.cfi_startproc
 2222              		@ args = 0, pretend = 0, frame = 0
 2223              		@ frame_needed = 0, uses_anonymous_args = 0
 2224              		@ link register save eliminated.
 2225              	.LVL111:
 538:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	reg32 *addrPort = &ISER0; 		// Pegar o endereço do registrador do periférico
 539:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	addrPort+=(reg32)(numIRQ/VIC_SIZE); 	// Determinar em que registrador pertence ao periférico
 2226              		.loc 1 539 0
 2227 0000 4309     		lsrs	r3, r0, #5
 2228 0002 9B00     		lsls	r3, r3, #2
 2229 0004 03F16043 		add	r3, r3, #-536870912
 540:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	*addrPort = (1 << (numIRQ%VIC_SIZE));	// Habilitar a pendencia interrupção do periférico
 2230              		.loc 1 540 0
 2231 0008 00F01F00 		and	r0, r0, #31
 2232              	.LVL112:
 2233 000c 0122     		movs	r2, #1
 539:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	*addrPort = (1 << (numIRQ%VIC_SIZE));	// Habilitar a pendencia interrupção do periférico
 2234              		.loc 1 539 0
 2235 000e 03F56143 		add	r3, r3, #57600
 2236              	.LVL113:
 2237              		.loc 1 540 0
 2238 0012 02FA00F0 		lsl	r0, r2, r0
 2239 0016 1860     		str	r0, [r3]
 2240 0018 7047     		bx	lr
 2241              		.cfi_endproc
 2242              	.LFE53:
 2244              		.section	.text.nvic_enableIRQ,"ax",%progbits
 2245              		.align	1
 2246              		.global	nvic_enableIRQ
 2247              		.thumb
 2248              		.thumb_func
 2250              	nvic_enableIRQ:
 2251              	.LFB59:
 2252              		.cfi_startproc
 2253              		@ args = 0, pretend = 0, frame = 0
 2254              		@ frame_needed = 0, uses_anonymous_args = 0
 2255              		@ link register save eliminated.
 2256 0000 FFF7FEBF 		b	nvic_setPendingIRQ
 2257              		.cfi_endproc
 2258              	.LFE59:
 2260              		.section	.text.nvic_clearPendingIRQ,"ax",%progbits
 2261              		.align	1
 2262              		.global	nvic_clearPendingIRQ
 2263              		.thumb
 2264              		.thumb_func
 2266              	nvic_clearPendingIRQ:
 2267              	.LFB54:
 541:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 542:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 543:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 544:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Descrição:	Desabilita a pendencia da interrupção de um determinado periférico
 545:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Parametro:	ID da interrupção do periférico
 546:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Retorna:		Nada
 547:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 548:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void nvic_clearPendingIRQ(u8 numIRQ) {
 2268              		.loc 1 548 0
 2269              		.cfi_startproc
 2270              		@ args = 0, pretend = 0, frame = 0
 2271              		@ frame_needed = 0, uses_anonymous_args = 0
 2272              		@ link register save eliminated.
 2273              	.LVL114:
 549:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	reg32 *addrPort = &ICPR0; 		// Pegar o endereço do registrador do periférico
 550:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	addrPort+=(reg32)(numIRQ/VIC_SIZE); 	// Determinar em que registrador pertence ao periférico
 2274              		.loc 1 550 0
 2275 0000 4209     		lsrs	r2, r0, #5
 2276              	.LVL115:
 551:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	*addrPort = (1 << (numIRQ%VIC_SIZE));	// Desabilitar a pendencia interrupção do periférico
 2277              		.loc 1 551 0
 2278 0002 0123     		movs	r3, #1
 2279 0004 00F01F00 		and	r0, r0, #31
 2280              	.LVL116:
 2281 0008 03FA00F0 		lsl	r0, r3, r0
 2282 000c 014B     		ldr	r3, .L359
 2283 000e 43F82200 		str	r0, [r3, r2, lsl #2]
 2284 0012 7047     		bx	lr
 2285              	.L360:
 2286              		.align	2
 2287              	.L359:
 2288 0014 80E200E0 		.word	-536812928
 2289              		.cfi_endproc
 2290              	.LFE54:
 2292              		.section	.text.nvic_getActiveIRQ,"ax",%progbits
 2293              		.align	1
 2294              		.global	nvic_getActiveIRQ
 2295              		.thumb
 2296              		.thumb_func
 2298              	nvic_getActiveIRQ:
 2299              	.LFB55:
 552:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 553:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 554:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 555:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 556:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Descrição:	Verifica se o a interrupção de um determinado periférico está ativa ou não
 557:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Parametro:	ID da interrupção do periférico
 558:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Retorna:		Retorna pdTRUE e a interrupção do periférico está ativa, senão pdFALSE
 559:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 560:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** u8 nvic_getActiveIRQ(u8 numIRQ) {
 2300              		.loc 1 560 0
 2301              		.cfi_startproc
 2302              		@ args = 0, pretend = 0, frame = 0
 2303              		@ frame_needed = 0, uses_anonymous_args = 0
 2304              		@ link register save eliminated.
 2305              	.LVL117:
 561:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	reg32 *addrPort = &IABR0; 			// Pegar o endereço do registrador do periférico
 562:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	addrPort+=(reg32)(numIRQ/VIC_SIZE); // Determinar em que registrador pertence ao periférico
 2306              		.loc 1 562 0
 2307 0000 4309     		lsrs	r3, r0, #5
 2308 0002 9B00     		lsls	r3, r3, #2
 2309 0004 03F16043 		add	r3, r3, #-536870912
 2310 0008 03F56343 		add	r3, r3, #58112
 2311              	.LVL118:
 563:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	return ( *addrPort & (1 << (numIRQ%VIC_SIZE)) )?pdTRUE:pdFALSE;
 2312              		.loc 1 563 0
 2313 000c 1A68     		ldr	r2, [r3]
 2314 000e 00F01F00 		and	r0, r0, #31
 2315              	.LVL119:
 2316 0012 0123     		movs	r3, #1
 2317              	.LVL120:
 2318 0014 03FA00F0 		lsl	r0, r3, r0
 2319 0018 1042     		tst	r0, r2
 564:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 2320              		.loc 1 564 0
 2321 001a 14BF     		ite	ne
 2322 001c 1846     		movne	r0, r3
 2323 001e 0020     		moveq	r0, #0
 2324 0020 7047     		bx	lr
 2325              		.cfi_endproc
 2326              	.LFE55:
 2328              		.section	.text.nvic_setPriority,"ax",%progbits
 2329              		.align	1
 2330              		.global	nvic_setPriority
 2331              		.thumb
 2332              		.thumb_func
 2334              	nvic_setPriority:
 2335              	.LFB56:
 565:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 566:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 567:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 568:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Descrição:	Ajusta a prioridade das interrupções dos periféricos ou do núcleo do ARM
 569:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Parametro:	ID da interrupção
 570:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //					Valores negativos são do núcleo do ARM, e os positivos são dos periféricos
 571:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //				Nível da interrupção
 572:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //					Para os periféricos de 0 a 31
 573:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Retorna:		Retorna pdTRUE e a interrupção do periférico está ativa, senão pdFALSE
 574:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------------------------------
 575:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void nvic_setPriority(s32 numIRQ, u8 priority) {
 2336              		.loc 1 575 0
 2337              		.cfi_startproc
 2338              		@ args = 0, pretend = 0, frame = 0
 2339              		@ frame_needed = 0, uses_anonymous_args = 0
 2340              		@ link register save eliminated.
 2341              	.LVL121:
 576:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#if (VIC_USE_DEBUG == pdON)
 577:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	plognp("set pri %d %u"CMD_TERMINATOR, numIRQ, priority);
 578:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	#endif
 579:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	if(numIRQ < 0) {
 2342              		.loc 1 579 0
 2343 0000 0028     		cmp	r0, #0
 2344 0002 C3B2     		uxtb	r3, r0
 2345 0004 4FEAC101 		lsl	r1, r1, #3
 2346              	.LVL122:
 2347 0008 0DDA     		bge	.L363
 2348              	.LVL123:
 2349              	.LBB2:
 580:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		reg32 *addrPort = &SHPR1; 				// Pegar o endereço do registrador do periférico
 581:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		addrPort+=(reg32)(((numIRQ&0xf)-4)/4); 	// Determinar em que registrador pertence ao periférico.
 582:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 												//   (numIRQ&0xf)-4 para converte o valor negativo
 583:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		// cada registrador de 32 bits, guarda a prioridade de 4 periféricos
 584:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		// logo cada byte é para cada periférico, então precisamo encontrar em que local [e
 585:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		reg8 *offset = (reg8*) addrPort;
 586:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		offset+=(reg8)((numIRQ&0xf)-4)%4;
 2350              		.loc 1 586 0
 2351 000a 00F00F00 		and	r0, r0, #15
 2352              	.LVL124:
 2353 000e 0422     		movs	r2, #4
 2354 0010 0438     		subs	r0, r0, #4
 2355              	.LVL125:
 2356 0012 90FBF2F0 		sdiv	r0, r0, r2
 2357              	.LVL126:
 2358 0016 03F00303 		and	r3, r3, #3
 587:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		*offset = ((priority << (8 - VIC_PRIO_BITS)) & 0xff);
 2359              		.loc 1 587 0
 2360 001a 094A     		ldr	r2, .L365
 586:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		*offset = ((priority << (8 - VIC_PRIO_BITS)) & 0xff);
 2361              		.loc 1 586 0
 2362 001c 03EB8003 		add	r3, r3, r0, lsl #2
 2363              	.LVL127:
 2364              		.loc 1 587 0
 2365 0020 C9B2     		uxtb	r1, r1
 2366 0022 9954     		strb	r1, [r3, r2]
 2367              	.LBE2:
 2368 0024 7047     		bx	lr
 2369              	.LVL128:
 2370              	.L363:
 2371              	.LBB3:
 588:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	} else {
 589:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		reg32 *addrPort = &IPR_BASE; 		// Pegar o endereço do registrador do periférico
 590:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		#if (VIC_USE_DEBUG == pdON)
 591:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		plognp("addrPort 0x%x"CMD_TERMINATOR, addrPort);
 592:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		#endif
 593:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		addrPort+=(reg32)(numIRQ/4); 		// Determinar em que registrador pertence ao periférico
 594:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		#if (VIC_USE_DEBUG == pdON)
 595:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		plognp("addrPort 0x%x"CMD_TERMINATOR, addrPort);
 596:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		#endif
 597:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		// cada registrador de 32 bits, guarda a prioridade de 4 periféricos
 598:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		// logo cada byte é para cada periférico, então precisamo encontrar em que local [e
 599:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		reg8 *offset = (reg8*) addrPort;
 600:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		#if (VIC_USE_DEBUG == pdON)
 601:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		plognp("offset init 0x%x"CMD_TERMINATOR, offset);
 602:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		#endif
 603:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		offset+=(reg8)numIRQ%4;
 2372              		.loc 1 603 0
 2373 0026 20F00300 		bic	r0, r0, #3
 2374              	.LVL129:
 2375 002a 03F00303 		and	r3, r3, #3
 2376 002e 1844     		add	r0, r0, r3
 2377 0030 00F16040 		add	r0, r0, #-536870912
 2378 0034 00F56440 		add	r0, r0, #58368
 2379              	.LVL130:
 604:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		#if (VIC_USE_DEBUG == pdON)
 605:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		plognp("offset 0x%x = 0x%x"CMD_TERMINATOR, offset, ((priority << (8 - VIC_PRIO_BITS)) & 0xff));
 606:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		#endif
 607:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 		*offset = ((priority << (8 - VIC_PRIO_BITS)) & 0xff);
 2380              		.loc 1 607 0
 2381 0038 C9B2     		uxtb	r1, r1
 2382 003a 0170     		strb	r1, [r0]
 2383 003c 7047     		bx	lr
 2384              	.L366:
 2385 003e 00BF     		.align	2
 2386              	.L365:
 2387 0040 18ED00E0 		.word	-536810216
 2388              	.LBE3:
 2389              		.cfi_endproc
 2390              	.LFE56:
 2392              		.section	.text.nvic_SetIntHandler,"ax",%progbits
 2393              		.align	1
 2394              		.global	nvic_SetIntHandler
 2395              		.thumb
 2396              		.thumb_func
 2398              	nvic_SetIntHandler:
 2399              	.LFB57:
 608:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	}
 609:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** }
 610:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 611:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 612:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // -----------------------------------------------------------------------
 613:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Descrição: 	Anexa uma routina para exibição de erro de interrupção
 614:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Parametro: 	int_func
 615:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //					Ponteiro da rotina que tratará o erro de vetor de interrupção
 616:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //					Ex:	nvic_SetIntHandler(showVicError);
 617:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //
 618:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //					Ex1:
 619:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //						void showVicError(int n) {
 620:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //							register_error_eeprom(n);
 621:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //							pisca_cod_led_xsegundos();
 622:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //							watchdogOn();
 623:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //							EsperarPeloResetDoWatchDog()
 624:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //						}
 625:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 
 626:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //					Ex2:
 627:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //						void showVicError(int n) {
 628:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //							static int x;
 629:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //							if (n>10) n=10;
 630:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //							while(1) {
 631:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //								for (x=0;x<n;x++) {	LED1_ON = LED1; delay_ms(250); LED1_OFF = LED1; delay_ms(250);}
 632:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //								delay_ms(1000);
 633:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //							}
 634:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //						}
 635:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** //						ATENÇÃO: NUNCA USA O DELAY COM INTERRUPÇÃO, USE A LIB COM LOOP, pois se este é um procedime
 636:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // Retorna:		Nada
 637:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** // ------------------------------------------------------------------------------------------------
 638:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** void nvic_SetIntHandler(void (*func)(int) ) {
 2400              		.loc 1 638 0
 2401              		.cfi_startproc
 2402              		@ args = 0, pretend = 0, frame = 0
 2403              		@ frame_needed = 0, uses_anonymous_args = 0
 2404              		@ link register save eliminated.
 2405              	.LVL131:
 639:uc_libc_dev/_arch/arm_lpc/common/vic_cortexm3.c **** 	vicerr_Functions = func;
 2406              		.loc 1 639 0
 2407 0000 014B     		ldr	r3, .L368
 2408 0002 1860     		str	r0, [r3]
 2409 0004 7047     		bx	lr
 2410              	.L369:
 2411 0006 00BF     		.align	2
 2412              	.L368:
 2413 0008 00000000 		.word	.LANCHOR0
 2414              		.cfi_endproc
 2415              	.LFE57:
 2417              		.global	gVectors
 2418              		.section	.vectors,"a",%progbits
 2419              		.align	2
 2422              	gVectors:
 2423 0000 00000000 		.word	_stack
 2424 0004 00000000 		.word	_start
 2425 0008 00000000 		.word	nmi_ISR
 2426 000c 00000000 		.word	hardFault_ISR
 2427 0010 00000000 		.word	memManage_ISR
 2428 0014 00000000 		.word	busFault_ISR
 2429 0018 00000000 		.word	usageFault_ISR
 2430 001c 00000000 		.word	0
 2431 0020 00000000 		.word	0
 2432 0024 00000000 		.word	0
 2433 0028 00000000 		.word	0
 2434 002c 00000000 		.word	svc_ISR
 2435 0030 00000000 		.word	debugMon_ISR
 2436 0034 00000000 		.word	0
 2437 0038 00000000 		.word	pendSV_ISR
 2438 003c 00000000 		.word	sysTick_ISR
 2439 0040 00000000 		.word	wdt_ISR
 2440 0044 00000000 		.word	timer0_ISR
 2441 0048 00000000 		.word	timer1_ISR
 2442 004c 00000000 		.word	timer2_ISR
 2443 0050 00000000 		.word	timer3_ISR
 2444 0054 00000000 		.word	uart0_ISR
 2445 0058 00000000 		.word	uart1_ISR
 2446 005c 00000000 		.word	uart2_ISR
 2447 0060 00000000 		.word	uart3_ISR
 2448 0064 00000000 		.word	pwm_ISR
 2449 0068 00000000 		.word	i2c0_ISR
 2450 006c 00000000 		.word	i2c1_ISR
 2451 0070 00000000 		.word	i2c2_ISR
 2452 0074 00000000 		.word	spi_ISR
 2453 0078 00000000 		.word	ssp0_ISR
 2454 007c 00000000 		.word	ssp1_ISR
 2455 0080 00000000 		.word	pll0_ISR
 2456 0084 00000000 		.word	rtc_ISR
 2457 0088 00000000 		.word	eint0_ISR
 2458 008c 00000000 		.word	eint1_ISR
 2459 0090 00000000 		.word	eint2_ISR
 2460 0094 00000000 		.word	eint3_ISR
 2461 0098 00000000 		.word	adc_ISR
 2462 009c 00000000 		.word	bod_ISR
 2463 00a0 00000000 		.word	usbHost_ISR
 2464 00a4 00000000 		.word	can_ISR
 2465 00a8 00000000 		.word	dma_ISR
 2466 00ac 00000000 		.word	i2s_ISR
 2467 00b0 00000000 		.word	enet_ISR
 2468 00b4 00000000 		.word	rit_ISR
 2469 00b8 00000000 		.word	mcpwm_ISR
 2470 00bc 00000000 		.word	qei_ISR
 2471 00c0 00000000 		.word	pll1_ISR
 2472 00c4 00000000 		.word	usbAct_ISR
 2473 00c8 00000000 		.word	canAct_ISR
 2474 00cc 00000000 		.word	uart4_ISR
 2475 00d0 00000000 		.word	ssp2_ISR
 2476 00d4 00000000 		.word	lcd_ISR
 2477 00d8 00000000 		.word	gpio_ISR
 2478 00dc 00000000 		.word	pwm0_ISR
 2479 00e0 00000000 		.word	eeprom_ISR
 2480              		.section	.rodata.str1.1,"aMS",%progbits,1
 2481              	.LC0:
 2482 0000 76696345 		.ascii	"vicErr NMI\000"
 2482      7272204E 
 2482      4D4900
 2483              	.LC1:
 2484 000b 76696345 		.ascii	"vicErr hardFault\012\000"
 2484      72722068 
 2484      61726446 
 2484      61756C74 
 2484      0A00
 2485              	.LC2:
 2486 001d 506F7373 		.ascii	"Possiveis causas:\012\000"
 2486      69766569 
 2486      73206361 
 2486      75736173 
 2486      3A0A00
 2487              	.LC3:
 2488 0030 20204163 		.ascii	"  Acesso a um hardware n\343o ligado ou com clock d"
 2488      6573736F 
 2488      20612075 
 2488      6D206861 
 2488      72647761 
 2489 0060 65736C69 		.ascii	"esligado\012\000"
 2489      6761646F 
 2489      0A00
 2490              	.LC4:
 2491 006a 20204163 		.ascii	"  Acesso a mem\363ria inexistente\012\000"
 2491      6573736F 
 2491      2061206D 
 2491      656DF372 
 2491      69612069 
 2492              	.LC5:
 2493 008a 20205265 		.ascii	"  Registrador acessando pino I/O apontando para dua"
 2493      67697374 
 2493      7261646F 
 2493      72206163 
 2493      65737361 
 2494 00bd 73206675 		.ascii	"s fun\347\365es diferentes\012\000"
 2494      6EE7F565 
 2494      73206469 
 2494      66657265 
 2494      6E746573 
 2495              	.LC6:
 2496 00d3 76696345 		.ascii	"vicErr memManage\000"
 2496      7272206D 
 2496      656D4D61 
 2496      6E616765 
 2496      00
 2497              	.LC7:
 2498 00e4 76696345 		.ascii	"vicErr busFault\000"
 2498      72722062 
 2498      75734661 
 2498      756C7400 
 2499              	.LC8:
 2500 00f4 76696345 		.ascii	"vicErr usageFault_ISR\000"
 2500      72722075 
 2500      73616765 
 2500      4661756C 
 2500      745F4953 
 2501              	.LC9:
 2502 010a 76696345 		.ascii	"vicErr svc\000"
 2502      72722073 
 2502      766300
 2503              	.LC10:
 2504 0115 76696345 		.ascii	"vicErr debugMon\000"
 2504      72722064 
 2504      65627567 
 2504      4D6F6E00 
 2505              	.LC11:
 2506 0125 76696345 		.ascii	"vicErr pendSV\000"
 2506      72722070 
 2506      656E6453 
 2506      5600
 2507              	.LC12:
 2508 0133 76696345 		.ascii	"vicErr sysTick\000"
 2508      72722073 
 2508      79735469 
 2508      636B00
 2509              	.LC13:
 2510 0142 76696345 		.ascii	"vicErr wdt\000"
 2510      72722077 
 2510      647400
 2511              	.LC14:
 2512 014d 76696345 		.ascii	"vicErr timer0\000"
 2512      72722074 
 2512      696D6572 
 2512      3000
 2513              	.LC15:
 2514 015b 76696345 		.ascii	"vicErr timer1\000"
 2514      72722074 
 2514      696D6572 
 2514      3100
 2515              	.LC16:
 2516 0169 76696345 		.ascii	"vicErr timer2\000"
 2516      72722074 
 2516      696D6572 
 2516      3200
 2517              	.LC17:
 2518 0177 76696345 		.ascii	"vicErr timer3\000"
 2518      72722074 
 2518      696D6572 
 2518      3300
 2519              	.LC18:
 2520 0185 76696345 		.ascii	"vicErr uart0\000"
 2520      72722075 
 2520      61727430 
 2520      00
 2521              	.LC19:
 2522 0192 76696345 		.ascii	"vicErr uart1\000"
 2522      72722075 
 2522      61727431 
 2522      00
 2523              	.LC20:
 2524 019f 76696345 		.ascii	"vicErr uart2\000"
 2524      72722075 
 2524      61727432 
 2524      00
 2525              	.LC21:
 2526 01ac 76696345 		.ascii	"vicErr uart3\000"
 2526      72722075 
 2526      61727433 
 2526      00
 2527              	.LC22:
 2528 01b9 76696345 		.ascii	"vicErr pwm\000"
 2528      72722070 
 2528      776D00
 2529              	.LC23:
 2530 01c4 76696345 		.ascii	"vicErr i2c0\000"
 2530      72722069 
 2530      32633000 
 2531              	.LC24:
 2532 01d0 76696345 		.ascii	"vicErr i2c1\000"
 2532      72722069 
 2532      32633100 
 2533              	.LC25:
 2534 01dc 76696345 		.ascii	"vicErr i2c2\000"
 2534      72722069 
 2534      32633200 
 2535              	.LC26:
 2536 01e8 76696345 		.ascii	"vicErr spi\000"
 2536      72722073 
 2536      706900
 2537              	.LC27:
 2538 01f3 76696345 		.ascii	"vicErr spp0\000"
 2538      72722073 
 2538      70703000 
 2539              	.LC28:
 2540 01ff 76696345 		.ascii	"vicErr spp1\000"
 2540      72722073 
 2540      70703100 
 2541              	.LC29:
 2542 020b 76696345 		.ascii	"vicErr pll0\000"
 2542      72722070 
 2542      6C6C3000 
 2543              	.LC30:
 2544 0217 76696345 		.ascii	"vicErr \000"
 2544      72722000 
 2545              	.LC31:
 2546 021f 76696345 		.ascii	"vicErr eint0\000"
 2546      72722065 
 2546      696E7430 
 2546      00
 2547              	.LC32:
 2548 022c 76696345 		.ascii	"vicErr eint1\000"
 2548      72722065 
 2548      696E7431 
 2548      00
 2549              	.LC33:
 2550 0239 76696345 		.ascii	"vicErr eint2\000"
 2550      72722065 
 2550      696E7432 
 2550      00
 2551              	.LC34:
 2552 0246 76696345 		.ascii	"vicErr eint3\000"
 2552      72722065 
 2552      696E7433 
 2552      00
 2553              	.LC35:
 2554 0253 76696345 		.ascii	"vicErr adc\000"
 2554      72722061 
 2554      646300
 2555              	.LC36:
 2556 025e 76696345 		.ascii	"vicErr bod\000"
 2556      72722062 
 2556      6F6400
 2557              	.LC37:
 2558 0269 76696345 		.ascii	"vicErr usb\000"
 2558      72722075 
 2558      736200
 2559              	.LC38:
 2560 0274 76696345 		.ascii	"vicErr can\000"
 2560      72722063 
 2560      616E00
 2561              	.LC39:
 2562 027f 76696345 		.ascii	"vicErr dma\000"
 2562      72722064 
 2562      6D6100
 2563              	.LC40:
 2564 028a 76696345 		.ascii	"vicErr i2s\000"
 2564      72722069 
 2564      327300
 2565              	.LC41:
 2566 0295 76696345 		.ascii	"vicErr enet\000"
 2566      72722065 
 2566      6E657400 
 2567              	.LC42:
 2568 02a1 76696345 		.ascii	"vicErr rit\000"
 2568      72722072 
 2568      697400
 2569              	.LC43:
 2570 02ac 76696345 		.ascii	"vicErr mcpwm\000"
 2570      7272206D 
 2570      6370776D 
 2570      00
 2571              	.LC44:
 2572 02b9 76696345 		.ascii	"vicErr qei\000"
 2572      72722071 
 2572      656900
 2573              	.LC45:
 2574 02c4 76696345 		.ascii	"vicErr pll1\000"
 2574      72722070 
 2574      6C6C3100 
 2575              	.LC46:
 2576 02d0 76696345 		.ascii	"vicErr USB ACT\000"
 2576      72722055 
 2576      53422041 
 2576      435400
 2577              	.LC47:
 2578 02df 76696345 		.ascii	"vicErr CAN ACT\000"
 2578      72722043 
 2578      414E2041 
 2578      435400
 2579              	.LC48:
 2580 02ee 76696345 		.ascii	"vicErr uart4\000"
 2580      72722075 
 2580      61727434 
 2580      00
 2581              	.LC49:
 2582 02fb 76696345 		.ascii	"vicErr ssp2\000"
 2582      72722073 
 2582      73703200 
 2583              	.LC50:
 2584 0307 76696345 		.ascii	"vicErr lcd\000"
 2584      7272206C 
 2584      636400
 2585              	.LC51:
 2586 0312 76696345 		.ascii	"vicErr gpio\000"
 2586      72722067 
 2586      70696F00 
 2587              	.LC52:
 2588 031e 76696345 		.ascii	"vicErr pwm0\000"
 2588      72722070 
 2588      776D3000 
 2589              	.LC53:
 2590 032a 76696345 		.ascii	"vicErr eeprom\000"
 2590      72722065 
 2590      6570726F 
 2590      6D00
 2591              		.section	.bss.vicerr_Functions,"aw",%nobits
 2592              		.align	2
 2593              		.set	.LANCHOR0,. + 0
 2596              	vicerr_Functions:
 2597 0000 00000000 		.space	4
 2598              		.text
 2599              	.Letext0:
 2600              		.file 2 "uc_libc_dev/_libdef/uc_libdefs.h"
 2601              		.file 3 "uc_libc_dev/stdio/stdio_uc.h"
DEFINED SYMBOLS
                            *ABS*:00000000 vic_cortexm3.c
D:\_temp\_windows\cczVQ2jk.s:20     .text.nmi_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:25     .text.nmi_ISR:00000000 nmi_ISR
D:\_temp\_windows\cczVQ2jk.s:57     .text.nmi_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:63     .text.hardFault_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:68     .text.hardFault_ISR:00000000 hardFault_ISR
D:\_temp\_windows\cczVQ2jk.s:119    .text.hardFault_ISR:00000038 $d
D:\_temp\_windows\cczVQ2jk.s:129    .text.memManage_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:134    .text.memManage_ISR:00000000 memManage_ISR
D:\_temp\_windows\cczVQ2jk.s:165    .text.memManage_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:171    .text.busFault_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:176    .text.busFault_ISR:00000000 busFault_ISR
D:\_temp\_windows\cczVQ2jk.s:207    .text.busFault_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:213    .text.usageFault_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:218    .text.usageFault_ISR:00000000 usageFault_ISR
D:\_temp\_windows\cczVQ2jk.s:249    .text.usageFault_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:255    .text.svc_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:260    .text.svc_ISR:00000000 svc_ISR
D:\_temp\_windows\cczVQ2jk.s:291    .text.svc_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:297    .text.debugMon_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:302    .text.debugMon_ISR:00000000 debugMon_ISR
D:\_temp\_windows\cczVQ2jk.s:333    .text.debugMon_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:339    .text.pendSV_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:344    .text.pendSV_ISR:00000000 pendSV_ISR
D:\_temp\_windows\cczVQ2jk.s:375    .text.pendSV_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:381    .text.sysTick_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:386    .text.sysTick_ISR:00000000 sysTick_ISR
D:\_temp\_windows\cczVQ2jk.s:417    .text.sysTick_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:423    .text.wdt_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:428    .text.wdt_ISR:00000000 wdt_ISR
D:\_temp\_windows\cczVQ2jk.s:459    .text.wdt_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:465    .text.timer0_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:470    .text.timer0_ISR:00000000 timer0_ISR
D:\_temp\_windows\cczVQ2jk.s:501    .text.timer0_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:507    .text.timer1_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:512    .text.timer1_ISR:00000000 timer1_ISR
D:\_temp\_windows\cczVQ2jk.s:543    .text.timer1_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:549    .text.timer2_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:554    .text.timer2_ISR:00000000 timer2_ISR
D:\_temp\_windows\cczVQ2jk.s:585    .text.timer2_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:591    .text.timer3_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:596    .text.timer3_ISR:00000000 timer3_ISR
D:\_temp\_windows\cczVQ2jk.s:627    .text.timer3_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:633    .text.uart0_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:638    .text.uart0_ISR:00000000 uart0_ISR
D:\_temp\_windows\cczVQ2jk.s:669    .text.uart0_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:675    .text.uart1_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:680    .text.uart1_ISR:00000000 uart1_ISR
D:\_temp\_windows\cczVQ2jk.s:711    .text.uart1_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:717    .text.uart2_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:722    .text.uart2_ISR:00000000 uart2_ISR
D:\_temp\_windows\cczVQ2jk.s:753    .text.uart2_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:759    .text.uart3_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:764    .text.uart3_ISR:00000000 uart3_ISR
D:\_temp\_windows\cczVQ2jk.s:795    .text.uart3_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:801    .text.pwm_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:806    .text.pwm_ISR:00000000 pwm_ISR
D:\_temp\_windows\cczVQ2jk.s:837    .text.pwm_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:843    .text.i2c0_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:848    .text.i2c0_ISR:00000000 i2c0_ISR
D:\_temp\_windows\cczVQ2jk.s:879    .text.i2c0_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:885    .text.i2c1_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:890    .text.i2c1_ISR:00000000 i2c1_ISR
D:\_temp\_windows\cczVQ2jk.s:921    .text.i2c1_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:927    .text.i2c2_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:932    .text.i2c2_ISR:00000000 i2c2_ISR
D:\_temp\_windows\cczVQ2jk.s:963    .text.i2c2_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:969    .text.spi_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:974    .text.spi_ISR:00000000 spi_ISR
D:\_temp\_windows\cczVQ2jk.s:1005   .text.spi_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1011   .text.ssp0_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1016   .text.ssp0_ISR:00000000 ssp0_ISR
D:\_temp\_windows\cczVQ2jk.s:1047   .text.ssp0_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1053   .text.ssp1_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1058   .text.ssp1_ISR:00000000 ssp1_ISR
D:\_temp\_windows\cczVQ2jk.s:1089   .text.ssp1_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1095   .text.pll0_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1100   .text.pll0_ISR:00000000 pll0_ISR
D:\_temp\_windows\cczVQ2jk.s:1131   .text.pll0_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1137   .text.rtc_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1142   .text.rtc_ISR:00000000 rtc_ISR
D:\_temp\_windows\cczVQ2jk.s:1173   .text.rtc_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1179   .text.eint0_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1184   .text.eint0_ISR:00000000 eint0_ISR
D:\_temp\_windows\cczVQ2jk.s:1215   .text.eint0_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1221   .text.eint1_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1226   .text.eint1_ISR:00000000 eint1_ISR
D:\_temp\_windows\cczVQ2jk.s:1257   .text.eint1_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1263   .text.eint2_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1268   .text.eint2_ISR:00000000 eint2_ISR
D:\_temp\_windows\cczVQ2jk.s:1299   .text.eint2_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1305   .text.eint3_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1310   .text.eint3_ISR:00000000 eint3_ISR
D:\_temp\_windows\cczVQ2jk.s:1341   .text.eint3_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1347   .text.adc_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1352   .text.adc_ISR:00000000 adc_ISR
D:\_temp\_windows\cczVQ2jk.s:1383   .text.adc_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1389   .text.bod_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1394   .text.bod_ISR:00000000 bod_ISR
D:\_temp\_windows\cczVQ2jk.s:1425   .text.bod_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1431   .text.usbHost_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1436   .text.usbHost_ISR:00000000 usbHost_ISR
D:\_temp\_windows\cczVQ2jk.s:1467   .text.usbHost_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1473   .text.can_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1478   .text.can_ISR:00000000 can_ISR
D:\_temp\_windows\cczVQ2jk.s:1509   .text.can_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1515   .text.dma_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1520   .text.dma_ISR:00000000 dma_ISR
D:\_temp\_windows\cczVQ2jk.s:1551   .text.dma_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1557   .text.i2s_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1562   .text.i2s_ISR:00000000 i2s_ISR
D:\_temp\_windows\cczVQ2jk.s:1593   .text.i2s_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1599   .text.enet_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1604   .text.enet_ISR:00000000 enet_ISR
D:\_temp\_windows\cczVQ2jk.s:1635   .text.enet_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1641   .text.rit_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1646   .text.rit_ISR:00000000 rit_ISR
D:\_temp\_windows\cczVQ2jk.s:1677   .text.rit_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1683   .text.mcpwm_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1688   .text.mcpwm_ISR:00000000 mcpwm_ISR
D:\_temp\_windows\cczVQ2jk.s:1719   .text.mcpwm_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1725   .text.qei_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1730   .text.qei_ISR:00000000 qei_ISR
D:\_temp\_windows\cczVQ2jk.s:1761   .text.qei_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1767   .text.pll1_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1772   .text.pll1_ISR:00000000 pll1_ISR
D:\_temp\_windows\cczVQ2jk.s:1803   .text.pll1_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1809   .text.usbAct_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1814   .text.usbAct_ISR:00000000 usbAct_ISR
D:\_temp\_windows\cczVQ2jk.s:1845   .text.usbAct_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1851   .text.canAct_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1856   .text.canAct_ISR:00000000 canAct_ISR
D:\_temp\_windows\cczVQ2jk.s:1887   .text.canAct_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1893   .text.uart4_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1898   .text.uart4_ISR:00000000 uart4_ISR
D:\_temp\_windows\cczVQ2jk.s:1929   .text.uart4_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1935   .text.ssp2_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1940   .text.ssp2_ISR:00000000 ssp2_ISR
D:\_temp\_windows\cczVQ2jk.s:1971   .text.ssp2_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:1977   .text.lcd_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:1982   .text.lcd_ISR:00000000 lcd_ISR
D:\_temp\_windows\cczVQ2jk.s:2013   .text.lcd_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:2019   .text.gpio_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:2024   .text.gpio_ISR:00000000 gpio_ISR
D:\_temp\_windows\cczVQ2jk.s:2055   .text.gpio_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:2061   .text.pwm0_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:2066   .text.pwm0_ISR:00000000 pwm0_ISR
D:\_temp\_windows\cczVQ2jk.s:2097   .text.pwm0_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:2103   .text.eeprom_ISR:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:2108   .text.eeprom_ISR:00000000 eeprom_ISR
D:\_temp\_windows\cczVQ2jk.s:2139   .text.eeprom_ISR:00000018 $d
D:\_temp\_windows\cczVQ2jk.s:2145   .text.nvic_disableIRQ:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:2150   .text.nvic_disableIRQ:00000000 nvic_disableIRQ
D:\_temp\_windows\cczVQ2jk.s:2172   .text.nvic_disableIRQ:00000014 $d
D:\_temp\_windows\cczVQ2jk.s:2177   .text.nvic_getPendingIRQ:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:2182   .text.nvic_getPendingIRQ:00000000 nvic_getPendingIRQ
D:\_temp\_windows\cczVQ2jk.s:2213   .text.nvic_setPendingIRQ:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:2218   .text.nvic_setPendingIRQ:00000000 nvic_setPendingIRQ
D:\_temp\_windows\cczVQ2jk.s:2245   .text.nvic_enableIRQ:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:2250   .text.nvic_enableIRQ:00000000 nvic_enableIRQ
D:\_temp\_windows\cczVQ2jk.s:2261   .text.nvic_clearPendingIRQ:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:2266   .text.nvic_clearPendingIRQ:00000000 nvic_clearPendingIRQ
D:\_temp\_windows\cczVQ2jk.s:2288   .text.nvic_clearPendingIRQ:00000014 $d
D:\_temp\_windows\cczVQ2jk.s:2293   .text.nvic_getActiveIRQ:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:2298   .text.nvic_getActiveIRQ:00000000 nvic_getActiveIRQ
D:\_temp\_windows\cczVQ2jk.s:2329   .text.nvic_setPriority:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:2334   .text.nvic_setPriority:00000000 nvic_setPriority
D:\_temp\_windows\cczVQ2jk.s:2387   .text.nvic_setPriority:00000040 $d
D:\_temp\_windows\cczVQ2jk.s:2393   .text.nvic_SetIntHandler:00000000 $t
D:\_temp\_windows\cczVQ2jk.s:2398   .text.nvic_SetIntHandler:00000000 nvic_SetIntHandler
D:\_temp\_windows\cczVQ2jk.s:2413   .text.nvic_SetIntHandler:00000008 $d
D:\_temp\_windows\cczVQ2jk.s:2422   .vectors:00000000 gVectors
D:\_temp\_windows\cczVQ2jk.s:2419   .vectors:00000000 $d
D:\_temp\_windows\cczVQ2jk.s:2592   .bss.vicerr_Functions:00000000 $d
D:\_temp\_windows\cczVQ2jk.s:2596   .bss.vicerr_Functions:00000000 vicerr_Functions
                     .debug_frame:00000010 $d

UNDEFINED SYMBOLS
rprintf
_stack
_start
